( DAC 11 Item 7 ) ----------------------------------------------- [06/16/11]
From: [ Asterix the Gaul ]
Subject: One engineer's notes on MENT's 9th annual ESL symposium at DAC'11
Hi John,
Anon pls.
Mentor just held its 9th annual ESL symposium on DAC Tuesday in San Diego.
With 376 attendees, up 49% compared to last year.
2011 San Diego 376 attendees
2010 Anaheim 248 attendees
Geographic breakdown of the attendees:
Europe : ##### 17%
Japan : # 3%
North America : ###################### 67%
PacRim : #### 13%
Previous ESL symposiums looked at how designers used ESL tools and their
flows. This year's symposium covered management's perspective on ESL.
Moderator:
Wally Rhines, CEO, Mentor Graphics
Panelists:
Gadi Singer, VP, Intel Architecture Group,
John Goodenough, VP of Design Technology, ARM
Ken Hansen, CTO, Freescale
Jean-Marc Chateau, Director, STMicroelectronics
Simon Bloch, GM, Mentor Graphics
GADI SINGER - INTEL
- ESL is at once: 1) Necessary, 2) About Time, and 3) Not enough yet
- Necessary: design complexity is now 3 orders of magnitude
more than when RTL was adopted
- About time: RTL was adopted decades ago, good ESL
capabilities have been available only since mid-2000's
- Not enough: golden reference point is not yet ESL model,
still is RTL. When can we use ESL as golden reference?
That is the key question.
- "ESL is a must have at Intel" for: pre-silicon SW development and
post-silicon readiness.
- Several High level synthesis (HLS) activities going on at Intel,
working well.
- HLS still needs: Standards; Improved ECO flow; Better ESL model
validation (we are spoiled from great quality/variety of RTL
verification methods); Formal checking between ESL and RTL;
SystemC linting; and Integration between HLS generated code and
hand-written RTL (because hand-written code will subsist for some
time).
- ESL sign-off needs are a rich language, an implementation path,
validation and formal verification, ECO - changes will come from
below. There are good ways to handle it in RTL, and the same is
needed for ESL.
- "We need ESL and we need more of it."
- An ESL success: Virtual prototype for early SW readiness.
JOHN GOODENOUGH - ARM
- ESL enables diversity, improves time to product. "It's all about
money."
- ESL covers multiple use cases.
- System Architecture Exploration
- SoC design and validation
- Application driven pre-silicon testing
- Pre-silicon bring-up
- App development post-silicon/product
- ESL is not magic. It brings tools to help through the design
process.
- Interoperability is crucial. Message to ESL community: Stop
having religion about one way of doing things. OSCI TLM 2.0
enables interoperability.
- Good adoption TLM 2.0 including new extension e.g. Direct Memory
- For processors debug interface also important e.g. CADI
- Profiling and Instrumentation still required
- Continuing Challenge running fast AND modelling Cycles on the Bus
- An ESL success: ESL was key in developing new multi-core and new
instruction set architecture.
KEN HANSEN - FREESCALE
- Case for ESL:
- Design complexity too great to optimize performance without ESL
- Customer demand a model for SW development prior to silicon
samples
- Freescale is using ESL to improve product competitiveness
- Architectural exploration to eliminate bottlenecks and produce a
better balanced design
- Enable internal SW development teams early in the design cycle
so that HW and SW can be married up timely to deliver first
samples
- HW/SW co-design feedback from SW developed on a virtual
prototype used to improve HW
- Beginning to use high-level synthesis (HLS) for developing
internal IP blocks
- Modeling is still the key bottleneck to broader adoption of ESL.
Until HLS technology improves to the point where the same model is
used for both HLS and VP, VP modeling is an added development cost.
"That's the elephant in the room."
- Multicore: there is a lot of work going in the interconnect
fabric. How do you feed the multiple cores? Memory bandwidth and
cache coherency are big factors and both are ESL problems.
Multicore device performance can be killed by poor SW code/
architecture. Need tools, cycle-accurate models to gain
visibility. The industry has no clue how to program multicore
devices.
- An ESL success: With ESL, delivered a virtual prototype 1 year in
advance of silicon, allowed booting Linux in days after first
silicon versus months.
JEAN-MARC CHATEAU - STMICROELECTRONICS
- Long tradition of ESL at ST, ST at the forefront of SystemC TLM and
IP-XACT
- ST's first ESL try was in the late 90's - tried to do cycle-
accurate platforms with CA models. Too slow to simulate and too
expensive to write/create. Then moved to TLM and gradually adopted
it. Milestones accomplished:
- 2002: Hardware IP verified before RTL freeze
- 2004: SystemC TLM models enabled subsystem verification (IP and
firmware) before RTL freeze and 6 months before silicon
- 2006: Hardware SoC integration verification before RTL freeze.
- 2008: Pre-pattern generation HW+SW product validation
preparation, Pre-RTL debug of SW/HW validation tests.
Pre-RTL software testing & debug for subsystems
- 2010: up to 6 months ahead of silicon for selected drivers
- 2011: HW/SW early performance estimates, Pre-silicon full SW
verification. Getting closer and closer, but not fully
there yet.
- HLS is fully deployed in volume at STMicro and ST-Ericsson. HLS
started in 2004 in central R&D Team, then in 2005 in consumer and
wireless multimedia divisions. Mostly used for multimedia and
video co-processors; HLS covers 80% of needs in this field.
- Today HLS is used for all internal IPs except: Network-on-Chip
(NoC), memory Interfaces (3rd party IP), and host interface
protocol handler
- HLS is 2-3x faster than writing RTL. Allows very fast creation of
derivatives, and easier and faster verification and validation (10x
less lines of code to maintain).
SIMON BLOCH - MENTOR GRAPHICS
- It's all about cost of design. As complexity increases, cost must
be kept stable to keep IC design affordable/economically viable.
- Top 3 drivers for ESL (according to 2010 survey data) are:
- Software validation 70%
- Faster verification & fewer bugs 62%
- Faster time to verified RTL 58%
- SoC design involves different engineering groups with different
goals and needs
- Hardware engineers want to reduce RTL design lead time
- Software engineers want to reduce code development and
verification time
- System Engineers want to find optimal SoC architectures
(power, performance, area)
- Verification engineers want better coverage with fewer
verification cycles
- There are different ESL subflows for each of these engineering
groups
- High level synthesis for hardware engineers
- Virtual prototyping for software engineers
- Architectural design and exploration for system engineers
- System verification for verification engineers
- State of ESL
- Technology is maturing
- HLS now capable of complete subsystem, including control,
interfaces and hierarchy, not just datapath/algorithms
- TLM is unifying ESL flows: virtual prototyping, architecture
exploration, system verification
- Many success stories published, strong sign of maturing flows
- SystemC provides the standards and the interoperability for
broader deployment
Wally concluded that this event served as a milestone indicating executive
management is championing ESL deployment.
- [ Asterix the Gaul ]
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