( DAC 12 Item 1 ) ----------------------------------------------- [09/20/12]
Subject: SpyGlass Power, PowerPro RTL, PowerArtist as #1 hot tool at DAC'12
TOLD YA SO: In the months before DAC there was a threeway battle on DeepChip
over RTL power optimization. Heck, I even chose these tools as my #1 in
my Cheesy Must See List. Now DAC'12 is over, and it's still anyone's guess
as to which specific tool is winning over the users in this race. All this
drama because PrimeTime-PX does gates and not RTL power opto!
Anyway, these three Atrenta/Calypto/Apache RTL power opto tools all taken
together were the #1 most interesting tools users saw at this DAC'12.
"What were the 3 or 4 most INTERESTING specific tools you
saw at DAC this year? WHY did they interest you?"
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Threeway tie on SpyGlass Power, PowerArtist, and PowerPro RTL
- [ An Anon Engineer ]
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RTL power analysis tools have gained lot of interest from designers.
PrimeTime-PX was a popular gate-level signoff analysis tool but is a
step "too-late" in the design cycle for useful power optimization.
The 2 main design goals of RTL power tools:
1. Power estimation of RTL
2. Power optimization of RTL
The RTL power tools featured at DAC 2012 were:
1. PowerArtist (Apache/Ansys)
2. SpyGlass Power (Atrenta)
3. PowerPro RTL (Calypto)
These were listed as the #1 tools on John's "must-see-list" for the DAC
2012 exhibits and I attended the customer sessions of the above three
RTL power tools. All three had many overlapping features and a thorough
testcase based evaluation is needed to really determine if one is ahead
of others in QOR.
1. PowerArtist (Apache/Ansys)
PowerArtist provides an accurate analysis at both RTL and gate level.
It also has optimization based on circuit structure and register
activity. WLM based RTL power estimate will be within 20% of gate
level power analysis with SPEF. For better accuracy (5% improvement),
a PACE model can be used instead of the WLM. Power optimization is
done on clock power, memory power and datapath power. The LNR (low
activity non-enabled register) optimization provides a significant
power saving.
PowerArtist can split wide memories to reduce memory power. It also
provides light sleep control and gating of redundant access. An
additional feature is that it generates a RTL power model that is
used by Redhawk for early Power Integrity analysis. There is a DIFF
power DB utility to compare what power changed during regressions.
The DB is based on OpenAccess and TCL API is available.
It needs a third party tool for an equivance check of sequential
clock gating correctness.
2. PowerPro RTL (Calypto)
PowerPro claims to have a better integrated power estimation and
optimization loop compared to others. It has accurate switching
activity propagation including the sequential switching activity.
Automatic power optimization is handled through PowerPro CG
(clock gate) and PowerPro MG (memory gate).
Powerpro CG not only inserts new enables but also strengthens
existing enables. MG extends memory inactive time and extends
light sleep periods. The PowerPro Adviser which guides advanced
optimization is the main strength of the PowerPro tool. It
provides new-enable expression optimization, mode signals and
the reasons for low clock gating efficiency.
It has a sequential logic equivalence checking tool (SLEC) for
initial RTL vs. power optimized RTL checks.
One shortcoming is that UPF/CPF is not yet supported.
3. SpyGlass Power (Atrenta)
For users of Spyglass RTL tools, SpyGlass Power would provide a
well integrated power analysis environment. The power data is
written into the same DB as the other RTL data. Spyglass power
also features validation of power information in the library
files and the power intent files.
It needs a third party tool for an equivance check of sequential
clock gating correctness.
All 3 tools feature sequential-analysis-based switching activity
propagation to determine the power saving opportunities.
There have been numerous user DeepChip discussions on RTL power tools
in ESNUG 500 #4, 500 #5, 501 #4, 501 #5, 502 #2, 505 #8.
- [ An Anon Engineer ]
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I was quite interested in Calypto PowerPro at DAC. We have a multi-
block system, with dozens of interconnected blocks.
PowerPro lets you analyze the power consumption of the individual
blocks at the RTL level. These power estimates let us to do system
level power analysis, which helps our architects to make
architectural decisions.
- [ An Anon Engineer ]
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Atrenta Spyglass Power has power analysis and guided optimization
to show you how to save power during RTL design.
I have never used it personally, but Atrenta's demo was good. The
tool is interesting and the dataflow is practical.
- [ An Anon Engineer ]
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Calypto PowerPro was interesting.
Especially PowerPro's advisor feature may be useful for our flow.
- [ An Anon Engineer ]
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RTL Power Reduction Tools at DAC 2012
As a personal comment, Apache Power Artist was originally developed
by Sequence which was later merged with Apache. Its users reported
the tool can give 3% to 10% power reductions. For low power designs,
it can read the power intent in either UPF or CPF. However, there
is no formal verification method to compare the original RTL with
the new power-optimized RTL generated by Power Artist. The user can
only use simulation method if for functional verification.
As for Calypto PowerPro, its users reported they get 9% to 12% power
reduction on Verilog RTL. However, its power reduction techniques
seem nothing special, probably because the tools were developed for
many years, when only a few tools addressed power issues. Besides,
PowerPro seems not taking multiple power domain nor power intent
into account.
On the other hand, it seems to me that Atrenta Spyglass Power provides
the most comprehensive solutions for RTL power reduction from what
I have seen in the demo as well as in the product literature. Unlike
the other two tools, it takes power intention via UPF/CPF into account
and also has sequential equivalent checking capability to formally
verify the input RTL source and the power-optimized RTL output
equivalent. As for power saving, Spyglass Power users reported the
tool can give 9% to 16% power reduction which is the highest number
among the three tools'.
One important note is, according to Atrenta, it does not seem the tool
gives much benefit for mobile chip designs, which I think it may be
applied to the other two tools. Therefore, without an evaluation on
our RTL codes, we cannot get a reasonable conclusion.
- [ An Anon Engineer ]
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I attended the Atrenta SpyGlass Power presentation at DAC'12.
SpyGlass Power has a complete feature set for RTL power analysis,
profiling and optimization. I also believe that its use of the
formal equivalency checking under-the-hood is very important for
SpyGlass Power tool adoption.
One of the features that are very useful is the ability to run RTL
peak power to identify the best spot in time (VCD) to run IR-drop
analysis, and also SDC generation is very useful.
- [ An Anon Engineer ]
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I saw Atrenta SpyGlass Power at DAC. Most noteworthy was its RTL
power analysis, and its memory power estimation features.
- [ An Anon Engineer ]
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