( DAC 12 Item 2 ) ----------------------------------------------- [09/20/12]
Subject: IP Central, Atrenta IP Kit, Sonics SGN as #2 hot tools at DAC'12
IP REUSE TOOLS: I gave IC Manage's "IP Central" and Atrenta's "IP Kit" as
a #1 in my Cheesy Must See List for 2011. It's nice to see they're getting
some traction this year. I also added SonicsGN because a user made a
strong case for it -- though I'm not sure if SGN is IP or an IP tool or a
mix of both -- plus Intel just bought $20 million of whatever it is.
These three: ICM IP Central, Atrenta IP Kit, Sonics SGN IP reuse tools all
taken together were the #2 most interesting tools users saw at DAC'12.
"What were the 3 or 4 most INTERESTING specific tools you
saw at DAC this year? WHY did they interest you?"
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I met with Sonics at DAC regarding their SonicsGN (SGN).
SGN is a network-on-chip (NoC) technology is used for high performance
interconnect. Sonics claims a 1 Ghz frequency. I haven't verified it.
I didn't investigate SonicsGN's low power aspects.
SonicsGN is a soft IP - they provide SystemC, RTL, verification and
synthesis scripts, etc. You provide inputs to configure your network
and then generate your network IP.
From a tool perpective, SGN's GUI and the approach was intuitive. I
liked that it allows a high level of system concurrency; supporting
a number of parallel transactions in a system. You can have multiple
transactions on the same port without any transaction pile-ups. This
increases network throughput without increase the number of wires.
SGN also helps you close timing, because it understands the placement.
It saves verification time because SGN generates the IP plus the
environment to verify that IP.
NOCS VS BUS MATRIX INTERCONNECTS
A great majority of people believe that a network on chip (NoC) is just
a bus matrix interconnect. This is not so. Below are the major
differences.
Bus Matrix Interconnects
- Traditional bus matrix interconnects are an antiquated view of the
world based on connecting a single processor to a single processor.
- With a bus matrix, everything is talking to everything - you just
configure a master/initiator and a number of targets/slaves, and the
addresses.
- You can build one yourself or buy a bus matrix interconnect IP from
Synopsys and ARM, but it's not very efficient for complex SoCs.
- Another big thing with this approach is that it takes a lot of
effort and iteration to close timing. And you end up having to
pipeline a lot of the buses which is bad for latency to actually
close the timing.
Network-on-Chips (NoC)
- A NoC is a smarter way to implement interconnect in terms of hardware
usage. If we define cores as any type of master (CPU, DMA, Micro DMA,
etc.) then 3-4 cores is probably the trigger point for an NoC to
become more suitable than a bus matrix. If we talk about CPU/GPU then
2 cores is where it start to make sense.
- You only connect what is needed, which lets you optimize tradeoffs
with latency, speed and power. For example Master 1 to targets/slaves
0,1,2,3; Master 3 to targets/slaves 2,3; master 0 to master 3.
- A NoC allows serialization.
SONICS GN VERSUS SONICS SX
Depending your design goal, you would use SonicsSX or SonicsGN.
- SonicsSX (SSX) provides parallel access to your addresses. The
latency is fast because all the data goes out at once, but you
have more wires.
- SonicsGN is a NoC. It is packet based - the header is serialized,
so you have fewer wires. SGN has higher frequency, and longer
latency than SSX. It also has more flexibility, faster throughput
and supports a bigger network.
Now we have complex systems where you must connect between nodes like a
Cisco router. (Muxing and decoding). So we'll be evaluating Sonics GN.
We will also evaluate Arteris' NoC technology.
- [ An Anon Engineer ]
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I met with IC Manage at DAC, and recently did some in-depth testing of
their IP Central tool for IP Reuse. (We already use GDP in house.)
1. IP Central Foreign Depot integration
We tested this. It works.
For the first time we can mix foreign depots/revision control system
(such as DesignSync, ClearCase, Subversion, Perforce) in IC Manage
and sync them. In our case our digital and software teams are on the
Perforce depot, while our analog group uses IC Manage.
This lets us freely swap data in all of our group.
Our analog design team can take delivery of and directly view data
from our digital and software teams, and use it in our designs. We no
longer have to email, FTP and copy files between the 3 teams. Once we
have hooks into the IC Manage depot, we can take any code and use it
inside IC Manage. We can communicate an issue/bug to the owner in the
digital group, they can change and update it in their own environment,
and we can see the updates in IC Manage seamlessly.
This multi-repository configuration management is good for IP reuse.
The IP/design module has a path and a history inside the depot, rather
than being checked in as a new object. When we make copies, the new
objects would be completely independent and all revision control history
links would be broken. In contrast, when we just send copies of an IP
via email, one version might get fixed but we can forget to update the
other copies floating around.
IC Manage uses virtual representation of objects. IP Central points
to the foreign depot and our project lead creates a virtual pointer
(marker) to the foreign depot object inside IC Manage and attaches the
pointer to the relevant project. Then designers can then sync their
workspace and see the data from the other design teams.
2. IP Central Bug Tracing/Management
IC Manage has a bug dependency management system which integrates with
Bugzilla and JIRA, but we don't use Bugzilla or JIRA. So we use
IC Manage's bug dependency management system in conjunction with our
own internal defect tracking system via the IC Manage "fix" command.
This should mean that IC Manage's bug dependency system would work with
any 3rd party defect tracker system without requiring customization.
IC Manage also claims it will work with properties, however I have not
verified this.
3. IP Central Properties
We are in the process of investigating and testing how well IP Central
properties work. Below are our areas of interest.
IP Central has a web interface portal to allow you to query and report
all the design project properties. You don't need IC Manage to view
the data using the IP Central web interface, so non-IC Manage users can
see project status.
We would like to track where our internal and external IP is being used
in all projects via a full catalog, so the IP Central querying aspect is
interesting to us.
We would also like to use IP Central to get up to the minute project
status. We want to understand the IP/module's development at each
stage, for example, to see if an IP block is ready/suitable to be
reused, LVS clean, DRC clean, DFM clean, if post-layout simulations have
been run and signed off, or some metric custom to a project.
We want to be able take any reused libraries or IP blocks (e.g. a std
cell library, PLL block, etc.):
- Assign properties which describe it.
- Have those properties transferred to all the projects
that use the library.
- We can go to a project and see all IP being used in a
project because the properties are attached to project.
- Use property triggers to query and see what stage each
project or IP is at by looking at the properties.
IC Manage says the properties can be attached to any level of a project
and be hierarchically inherited.
- [ An Anon Engineer ]
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IC Manage IP Central for IP reuse, and bug tracing/management.
As you can imagine, any IP business is interested in both of those.
- [ An Anon Engineer ]
---- ---- ---- ---- ---- ---- ----
I saw the Atrenta IP Kit at DAC. You use it to define your own metrics
for IP quality and set up checks as you do your design. The IP Kit
creates a summary report on your IP, including how it meets different
metrics and constraints and reports how many errors/warnings are
associated with the IP.
You have to use Atrenta's tools to generate these "IP qualify" reports.
Since we don't use only Atrenta's tools for verifying our IP, we can't
yet use their IP Kit to generate a summary report for IP release.
- [ An Anon Engineer ]
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After chatting with Atrenta, I decided to take a look at "GenSys" which
is used to assemble IP into RTL code.
Since it is very difficult for us to know in advance how much power for
MBIST, at our best, we can simply design a programmable BIST controller
to decide later how many BISTs we can turn on per batch.
We are looking for solutions to insert IP test logic into RTL code. If,
as advertised, we can specify it in IP-XACT, and GenSys can perform RTL
insertion and provide test bench to run simulation on RTL, it would be
good.
- [ An Anon Engineer ]
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