( DAC'13 Item 3 ) ----------------------------------------------- [09/27/13]
Subject: Calypto PowerPro vs. Atrenta Spyglass Power was #3 at DAC'13
CALYPTO KICKS ASS: Last year there was a very public threeway battle at DAC
between Apache PowerArtist, Atrenta Spyglass Power, and Calypto PowerPro in
RTL power optimization. See #1 in my Cheesy Must See List for DAC'12.
This year, judging from the user comments, it appears that Calypto PowerPro
has won this fight, with Atrenta Spyglass Power coming in at #2 with a few
supporting user votes -- and with Apache PowerArtist completely Missing In
Action (M.I.A.) -- with not one customer advocating for it.
On the tech side, one big thing that differentiates Calypto PowerPro from
its rivals is its deep hooks with the Calypto SLEC tool. Maybe that's
enough to tip the scales in their favor?
On the business side this Apache absence is no surprise; the rumor mill has
been saying their staff has pulled waaaaaaaay back in the past 12 months as
they get absorbed into the Ansys mothership. (See botton of ESNUG 531 #4)
Why Atrenta Spyglass Power came in as a weak #2 is anybody's guess.
"What were the 3 or 4 most INTERESTING specific tools you
saw at DAC this year? WHY did they interest you?"
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Calypto PowerPro and SLEC
PowerPro is probably the only tool in the market today that does
sequential clock gating and memory gating optimizations.
Clock-gating has become pervasive in digital designs to the point
that both Design Compiler and RTL Compiler do combinatorial clock
-gating insertion. Sequential clock-gating requires state tracking,
but it pays dividends in a massively pipelined design.
We've seen good incremental clock-gating on our pipeline registers
with PowerPro.
To validate the correctness of this sequential clock gating, we use
Calypto SLEC. Cadence LEC and Synopsys Formality can't perform
equivalence check across sequential boundaries.
This is something unique in Calypto's portfolio.
---- ---- ---- ---- ---- ---- ----
Calypto PowerPro
It can be used to understand and improve clock-gating as well as
memory-gating efficiency of our Verilog RTL designs.
PowerPro identifies MUXed outputs so as to gate their previous stages
that may be switching unnecessarily. It also finds stable signals
so it can gate downstream stages that might be switching as well.
The newly identified gating-logic along with the original RTL is
written out for user to consider, along with reports on clock-gating
efficiency and register power.
It also allows for performing sequential LEC against the original RTL
using its own SLEC engine. Timing critical signals can be marked by
the user or through timing reports so they are not used in generating
gating signals.
We like our RTL and physical design folks to understand potential
clock-gating opportunities in their design that ultimately leads to
sizeable power savings.
---- ---- ---- ---- ---- ---- ----
I attended Calypto PowerPro session and was impressed in general with
what they had to offer. The only downside that I saw was that the
optimizations required to a great extent its own SLEC checker.
---- ---- ---- ---- ---- ---- ----
We have already applied Calypto PowerPro to our projects.
Calypto plans to release the next version to support power reduction
from the architecture-level and to reduce the running time from
RTL-modification-to-estimation.
This is helpful for us to reduce more dynamic power consumption in
our next projects.
---- ---- ---- ---- ---- ---- ----
Calypto PowerPro is an automated way to check for power savings and
it is valuable for pointing to areas of the design that can be
improved, either automatically or manually by our circuit designer.
It's useful extra tool/check for high-performance design.
---- ---- ---- ---- ---- ---- ----
I liked Calypto PowerPro at this DAC.
They use a sequential formal equivalence engine to find potential
optimizations across multiple clock periods - e.g. identifying
areas where data can be gated earlier in the pipeline to avoid
unnecessary toggling (of both data and clock paths).
Armed with this, the user can chose to have PowerPro automatically
edit his RTL (with inline comments to identify the changes and its
reasoning) or to give feedback to the original RTL engineer to get
his input.
I was also impressed by the added Calypto paper by AMD.
We haven't had time to evaluate the tool (it's been tapeout hell
since DAC) so we can't comment on how much power could be saved
for the next design - but it's definitely worth a look.
---- ---- ---- ---- ---- ---- ----
I thought Calypto PowerPro's session at DAC was informative. The
AMD speaker gave a detailed description of the role played by
Calypto tool in optimizing RTL to make the design power efficient.
He shared the results of his project -- and compared the power
improvements obtained with and without the tool.
Overall the AMD session was good. He could have approached the
topic in a more generic manner vs. being wholly project-centric.
---- ---- ---- ---- ---- ---- ----
At DAC I did attend a session on Calypto PowerPro.
Being able to both get accurate power numbers early in the design
process and get a "free" power seems very attractive.
We plan on evaluating PowerPro (and their SLEC equivalence checker)
to get a more in depth understanding of its capacities.
---- ---- ---- ---- ---- ---- ----
Calypto PowerPro's clock-gating looked interesting to me.
We have the tool in-house now, but I haven't tested it yet.
---- ---- ---- ---- ---- ---- ----
We did a comparative analysis on Calypto vs. Atrenta for Verilog
RTL power reduction and found:
Calypto PowerPro was superior when it comes to RTL-level power
reduction. PowerPro identified many more moves compared to
Spyglass Power and it translated into higher dynamic power savings
for us after physical implementation.
Calypto's aggressive optimization needs to be curbed in timing
critical parts of the design.
Atrenta Spyglass is ahead when it comes to RTL power estimation.
However, Spyglass accuracy (w.r.t gate-level estimates) is still
not as good as one would expect.
Calypto is way behind purely on the basis of RTL power estimation.
---- ---- ---- ---- ---- ---- ----
Atrenta SpyGlass Power adds RTL- and gate-level average power
estimation that uses the same proven Atrenta lint infrastructure.
There is no reason now not to know and track power of the design
throughout the whole design process.
---- ---- ---- ---- ---- ---- ----
Atrenta Spyglass Power
---- ---- ---- ---- ---- ---- ----
3. Low Power Verification (good tools from Synopsys and Cadence)
---- ---- ---- ---- ---- ---- ----
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