( DAC'13 Item 5 ) ----------------------------------------------- [09/27/13]
Subject: CLK-DA AOCV FX, Excellicon, Nangate, Dorado were #5 at DAC'13
TWEAKERS: Any chip designer with at least 6 months of on-the-job experience
will tell you that although synthesis, P&R, STA, noise, DRC, etc. gets you
90% or 95% or even 99% of the way to final sign-off -- there's always *some*
something(s) you gotta tweak to get to that best possible chip.
At this year's DAC, engineers voted CLK-DA for AOCV/POCV, Nangate for std
libs, Dorado for ECO's, and a whole bunch of them vouched for Excellicon for
constraints -- while FishTail got one honorable mention, as tweaker tools.
"What were the 3 or 4 most INTERESTING specific tools you
saw at DAC this year? WHY did they interest you?"
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We found CLK-DA's AOCV FX can be a potentially useful tool for our
high performance designs.
It generates instance-specific derate data and is fast compared to
the add-ons PrimeTime has.
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CLK-DA will be able to make a nice niche for themselves in the
expanding and increasingly critical area of AOCV/POCV coefficient
generation.
Their primary advantage in this space is the rapid turn-around
time for generating the table coefficients using their proprietary
modeling capabilities. PrimeTime needs this.
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I am currently running an eval of CLK-DAs critical path analysis
tools. Although I think it is too soon to come to any conclusion
regarding their suitability for our purpose, which is to time
through & characterize full custom logic structures using their
Path FX tool.
What I can say is that although they claim to be able to write
Liberty format NLDMs, I have run into quite a few issues reading
those models into PrimeTime.
To me this either means Synopsys is not adhering to the true
Liberty standard, -- or CLK-DA is making up their own Liberty
constructs. I suspect the truth is somewhere in between.
I'm pretty happy with CLK-DA's technical support so far.
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Nangate Library Creator
CLK-DA AOCV FX
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CLK-DA >> Ease of generation of AOCV tables
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Dorado ECO:
Impressive Tweaker tool. Reads in all the available data to create
ECOs, fixes are layout friendly, routing aware.
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b. Excellicon : Constraints Manager and Constraints Certification
tools -- ConMan / ConCert.
User friendly, thorough, high capacity tool addressing the pain points.
Today many designs only have IP integration troubles because their
constraints go through many hands and not everybody understands the
constraints. ConMan and ConCert help deal with this.
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1. Excellicon ConMan/ConCert 2. Oasys RealTime 3. Cadence Tempus
Excellicon had the best suite of tools available for SDC Generation and
Verification.
I am a user of Fishtail tools (Focus, Refocus and Confirm) and although
Fishtail is good in exception generation, it does not do a good job for
the rest of the SDC.
In contrast, Excellicon ConMan & ConCert can do anything to do with
timing constraints. Its clock extraction is robust. They also
automatically extract all the modes and derive case_analysis.
I am currently evaluating ConMan and comparing it against Fishtail.
The debug part of both ConMan and ConCert is built using formal so the
what-if-analysis is very good. Plus, it is very nicely integrated
with Verdi. Nice tools.
As to Oasys Realtime and Cadence Tempus, it is their runtime attract me.
It can save time and money but designs.
Ausdia's TimeVision. Rudimentary GUI and patchwork scripts. I heard
from my friends that their tool is not stable and crashes a lot.
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Fishtail >> b'cos of claim it'll generate "less noise" & hence, use
less of engineer's time!
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I was looking for tools for the following.
1. SDC certification
2. Early power analysis
3. PNR database viewer
4. ECO
On SDC certification the best tools I found out there were Excellicon.
Concert covered most of the issues we cared about such as:
1. Clock Discovery: All clocks in the design including generated
clocks with correct relations
2. Mode Discovery: the ability to synthesize modes automatically
3. Powerful SDC analysis and debug using formal methods, through
GUI or Tell Shell
4. Clocking structure GUI using formal methods for what-if-analysis
5. Single database for SDC management and synthesis of Multi-Mode
SDC for any layer of hierarchy
I also liked Conman for the ability to generate SDC. We have some
legacy blocks for which the designer is no longer around. We would
like to generate SDC for these. Conman is a great help in this case.
The other SDC verification tools I looked at were AUSDIA, Fishtail,
and, of course, Spyglass.
All of them were in the same mold with slight differences except for
Concert. This was the stand out best I have seen.
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ConMan by Excellicon
Does timing constraints generation, validation and timing closure. I
saw Spyglass-Constraints, Fishtail products and even Ausdia Timevision.
However, by far Excellicon's products impressed me the most.
ConMan can takes RTL or gates and extracts all clocks, clock groups,
IO's with related clocks, FP's & MCP's, all DRC's and even synthesize
case_analysis values. The last part is the most interesting as this
is what takes most of the time when coding SDC's. ConMan writes out
SDC in single mode, merged mode, partial merging, SDC's with some
modules treated as .lib models, SDC's for power analysis or CDC
analysism etc.
It seemed to me that Ausdia and Fishtail are weak in full spectrum of
Constraints, with Ausdia focused primarily on clock exceptions and
Fishtail on data exceptions.
With ConMan (I spent an hour with these guys going over the demo), all
modes were discovered right up front. Complete SDC was generated with
correct clock and data exceptions etc. The clocking structure was also
represented in a Google Map like diagram which makes it very simple to
understand. Good tool, I was really impressed.
Heard about ConCert and ConStar but did not see the demo. Apparently,
ConCert is a SDC verification tool which writes out incremental SDC if
the original SDC is incorrect or incomplete.
ConStar is a timing analysis tool and publishes MCMM reports.
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ConMan from Excellicon.
We been having few issues with constraint generation.
We had few chips taped out with incorrect or missing constraint which
cost us dearly.
This tool is constraint generation/verification.
Any hierarchy SDC generation, what-if analysis capability, and full
chip clocking visualization were interesting aspects of the tool.
Check it out.
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Excellicon ConMan & ConCert
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Best Tool was from Excellicon. I really liked the ConMan constraints
compiler. It automatically determine the modes in a design. It
synthesizes the case_analysis values and generates multi-mode
constraints.
It's analysis and debug capability of a design through the clock
browser GUI is amazing.
ConCert is their other tool which does SDC verification. It's more
comparable to what Atrenta, Fishtail and Ausdia offer. However, I
liked the simplicity of this tool and low noise output since they use
formal technology that cuts out all the noise from the reports.
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