( DAC 13 Item 6 ) ----------------------------------------------- [10/15/13]
Subject: Calypto Catapult HLS trounces Forte, C-to-S, and SNPS at DAC'13
CALYPTO KICKS ASS (PART II): Not only did Calypto do well with DAC attendees
in the RTL optimization niche, it appears that Calypto has also embarrassed
its usual C++/SystemC/ANSI C synthesis rivals this year, too. Catapult HLS
got 12 user "Best of DAC'13" -- while Forte Cynthesizer got only 2 mentions,
Cadence C-to-Silicon just one mention, and Synopsys Synfora SystemC Compiler
got nada. (Oops!) Maybe SLEC, their SystemC-to-Verilog/VHDL RTL sequential
equivalency checker, is giving Calypto enough of a competitive edge here???
Poor Brett! Now I must ask if Gary Smith's Market Trends will be reporting
the 2013 HLS marketshare shifted back to CatapultC -- at Forte's expense two
years from now? (Ouch!)
"What were the 3 or 4 most INTERESTING specific tools you
saw at DAC this year? WHY did they interest you?"
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I like the Catapult HLS and SLEC integration.
It's useful for C-to-RTL equivalency, eliminating the need for
complex testbench development, but even more important for
C-to-C equivalency after clock gating at C level of hierarchy.
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I've been using Catapult for last 5 months doing high level synthesis
of SystemC vision DSP algorithms.
Catapult allows me to do a microarchitecture design exploration,
helping to understand how the structures are choosing from a specific
std cell library to meet target frequency, latency and area.
I've had huge algorithms in SystemC and the RTL generated by Catapult
simply PASSED in testbench verification FIRST time without any fixes!
It let's me get a quick RTL implementation, handles the finite
representation, defines the timing schedule between the algorithms
functions within several module instances. Doing everything like this
by hand this would take too much time and be almost impossible to have
work without any fixes in a short project time frame.
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We had a good meeting at DAC with Calypto on Catapult. We got to see
their Bluebook on high level syntheses methodology and coding style,
which looks useful.
We also discussed Calypto SLEC C-to-RTL equivalency checking.
We currently use Catapult C but not SLEC.
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I learned at DAC that Calypto is moving to more tightly integrate
Catapult HLS and SLEC equivalence checking.
This is a good idea.
The only downside of this integration is that other HLS tool
vendors like, Forte and Cadence, are unlikely to partner with
Calypto in using SLEC as their complimentary equivalence
checking solution.
However, this downside was already there when Calypto acquired
Catapult HLS.
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Catapult LP
My focus during the presentation was on the questions regarding
low power and function parallelization. The tool changes parallelism
in the function (adds resources to make it more parallel) only if the
power constraint allows us.
The speaker showed demos that, yes, it could be done.
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I am very interested in HDL code generation with tools like Catapult
HLS and SLEC equivalency checking because I think they might replace
the traditional HDL design flow.
I cannot give more feedback because I did not run an evaluation on
Calypto tools. I am in touch with Calypto people to make it happen.
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My impression is that the support for low power is the most attractive
part in Catapult HLS. Calypto seems good in this aspect. Their SLEC
might give them an advantage vs. their rivals.
However, I did not get statistical data on the latency and area savings
from Calypto.
Another concern is that there might be lot of training required on
using their HLS tool.
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The Calypto Catapult HLS demo showed how to synthesize SystemC to RTL
and how to write synthesizable SystemC code. Unfortunately, they did
not show their advantages over similar products from other companies,
e.g., Xilinx Vivado HLS.
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Calypto SLEC sounds quite compelling.
I'm a manager though, not a user, and we're not using Calypto (yet),
so I can't provide additional technical insights.
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Calypto Catapult HLS
Are there any automatic optimizations for loop transformation and
memory-access optimization when doing high-level synthesis? For
example, loop pipelining, loop unrolling, loop tiling, memory
partitioning, data reuse, etc. ?
Catapult HLS seemed improving the performance and power of your HW
implementation, but I didn't see any introduction of the above in
their slides. I think customers will care about what kind of
high-level optimizations the tool can do, otherwise they will have
to do it manually by themselves.
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I thought Calypto's tools were impressive, based on the presentation.
I have no direct experience with C/C++/SystemC tools, and do not expect
to get any soon, so I cannot say how they measure up in practice to the
claims made during the presentation.
The main thing I noticed about Calypto was the amount of resources they
put into DAC. They had their name on the lanyards given to attendees,
sponsored other parts of the conference, and had a large exhibition
floor suite with at least four presentation rooms. I am sure that none
of that came cheap.
The expenditure seemed out of proportion, given the size of the markets
they are chasing.
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Forte and Calypto
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Forte Cynthesizer 5:
Their big claims are:
- New synthesis algorithms (code name is "C5")
- Updated GUI
- Low power synthesis capability
There were several new claims for the new synthesis algorithms but it
was difficult to understand the user benefit. The claim is that v5.0
reduce area by 6% on average and should run faster. We will have to
try it on our designs and report back.
Forte also created a new GUI. The old GUI looked some problems. The
new one seems to be better.
The most important update was about Forte's low power synthesis. Forte
claims that there are several optimizations their tool can do better
than RTL designers. Does optimized clock-gating, minimize registers
and datapath switching. Claim is 35% reduction in power and they
showed some sample designs. It was not clear to me exactly how this
was measured.
Forte also claims to have a patent on some kind of FSM optimization.
It optimizes the state encoding to minimize the number of bits that
transition without going to full one-hot encoding. I don't know if
this will have much value in our applications right now.
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Cadence C-to-Silicon
They showed a complicated Data Access Controller design from Fujitsu;
compared with handwritten RTL, Line Count of 1/3, 35% better timing,
35% area reduction and 51% dynamic power reduction with 8 channels
at 400 Mhz.
I liked their SystemC white-box monitoring to observe internal
activities inside a model during simulation. Cadence wb_lib also works
for private members of SystemC classes, local variables of functions,
primitive C++ data types, SystemC data types or user-defined classes.
The demo illustrated a consistent verification flow for a PL330 DMAC
model from TLM to RTL level. Did verification of the HLS model in
Cadence Virtual System Platform. They showed that their HLS model
could be configured with a TLM2 interface to offer the high simulation
speed when validating software, but also a pin level, signal level RTL
interface to verify the correctness of lower level interface protocols.
They showed their AXI3 lib, how the API of an initiator with access to
5 AXI channels can be configured with signal mode to access the pins
and be synthesized by CtoS, but also with TLM1 mode to implement FIFO
accesses and TLM2 to create TLM2 data and call TLM2 transport.
Live demo of the TLM-GDSII ECO capabilities with only 1 line changed
in SystemC, 2 lines in the generated RTL, 5 items changed in the ECO
netlist and 1 single inverter placed on "mode_in" in the P&R netlist.
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