( DAC'14 Item 1 ) ----------------------------------------------- [12/05/14]
Subject: Mentor Veloce vs. Cadence Palladium was #1 hot tool at DAC'14
TALE OF TWO EMULATORS: A quick recap of the MENT Veloce vs. CDNS Palladium
wars for the past 3 years. 30 Months ago Greg and Wally bragged:
MENT bigwigs say Veloce 2 will pass CDNS Palladium by end-of-year
Then 9 months ago, Gary Smith said 42% Veloce vs. 58% Palladium:
Oops! Gary Smith's data shows Wally and Greg wrong on emulation
Then 3 weeks ago, Jay Vleeschhouwer said 56% Veloce vs. 44% Palladium:
Wall St. says Wally and Greg right on emulation plus Intel scoop
And interestingly enough, the users comments pretty much also paralled this
neck-on-neck horse race with most engineers choosing either Veloce or
Palladium as their choice for "Best of DAC" -- that is, right now MENT
appears to be leading -- but it's way too early to say that CDNS has been
knocked out. It's neck-on-neck between MENT and CDNS.
  
Two odd side footnotes: The first is a few users also cited the new Cadence
Protium FPGA prototyper -- which I thought was under NDA during the DAC.
The other weird story -- which I don't quite understand -- is hardly anyone
mentions Synopsys EVE Zebu nor Synopsys HAPS in all these emulation and/or
acceleration and/or prototyping discussions!?! Huh?
SURVEY QUESTION #1:
"What were the 3 or 4 most INTERESTING specific EDA tools
you saw at DAC this year? WHY did they interest you?"
---- ---- ---- ---- ---- ---- ----
Veloce - flexible configuration emulator with big capacity, and
friendly GUI. Codelink for SW debug, UPF based low power design
verification.
---- ---- ---- ---- ---- ---- ----
I evaluated the Mentor Veloce at our company for roughly 6 months
in 2014. I ran several large PCI Express designs on it and had a
good experience with it.
Support was good when it was needed. We will continue using it.
---- ---- ---- ---- ---- ---- ----
Until we got access to an emulator, we were barely making progress
on chip-level testing of our 32x100G SDN chip. To our surprise,
Veloce swept us off our feet -- a week of simulation time replaced
by a few hours of emulation time and we were sold!
Since we (verification team) had built a stable environment, we then
had the chance to bring up our chip using our software suite inside
Veloce. Flushed out our early chip programming issues.
---- ---- ---- ---- ---- ---- ----
We've used Veloce Soft Models, Virtual Transactor IP and debug
tools. It models realistic scenarios, boots operating systems,
and we develop software stacks with it.
---- ---- ---- ---- ---- ---- ----
This was the first time we tried emulation. Our experience with
Veloce was very positive. We were able to get our chip up and
running on the emulator with a completely synthesized testbench,
everything in-the-box, with good performance.
We used Veloce in hybrid mode. For example, where we had a live
JTAG connection to external world while being able to boot Linux
from a soft model with UARTS dumping output to a log file.
Our chip being a new architecture this was very critical. We
used couple of Mentor's external peripheral models with Veloce.
After the tapeout multiple instances of the emulator were used
heavily by our software/driver/bringup team to develop new
drivers/debug their software.
When our chip came back SW was ready to go. Everything worked!
We were able to show our fully working chip to the external world
at a trade show a week after we got our hands on it.
---- ---- ---- ---- ---- ---- ----
We use Veloce emulation around the clock to verify our designs.
It's good for corner cases where it is either difficult or
impossible to capture in simulation.
Besides ICE, their speedbridges, Codelink, memories, TBX are
also pretty good.
---- ---- ---- ---- ---- ---- ----
Mentor's Veloce2. Mentor has made lots of headway since the launch
of Veloce in 2007, both in terms of expanding its customer base and
enhancing the product. At DAC, they presented its new OS3 emulation
operating system. Veloce compile and debug are comparable with
Palladium.
Mentor has added applications for low power, functional coverage in
emulation, software debugging via Codelink without the intrusiveness
of a JTAG approach. VirtuaLAB is their virtual environment that
runs as fast as ICE without the manual supervision of ICE. They can
do remote access emulation data centers because of this.
---- ---- ---- ---- ---- ---- ----
Palladium XP2 - co-emulating with ARM fast models, plus its offline
debug, plus forward/rewind without re-running was interesting.
Their ICE now does "in circuit in a box": workstations with all the
software, OS, drivers and speedbridge cards attached.
Nvidia and CSR spoke. AMD also spoke on power event monitoring.
---- ---- ---- ---- ---- ---- ----
Cadence's Palladium-XP-2. Very fast compilation time and good debug
because of its custom-processor technology. However, it is still
built on the same basic hardware. Similar speed and only slightly
more capacity than XP.
At DAC, Cadence showed hybrid emulation consisting of interfacing
the emulator to a virtual test environment, based on a transaction
communication interface. Cadence outshines Veloce and Zebu with its
in-circuit-emulation (ICE) with a massive catalog of speed bridges.
Despite its marketing, also Palladium-XP2 lags behind Veloce in
transaction-based acceleration (TBA), and is rumored to be rather
slower than ICE. In earnings calls, Lip-Bu claims progress in TBA.
To me, it sounds like an admission of a weakness.
---- ---- ---- ---- ---- ---- ----
Cadence Rapid Prototyping Platform -- recently renamed to "Protium".
FPGA prototyping. Claims of getting into this FPGA system from a
Palladium database. Low cost, faster bringup.
Jury is still out and Cadence definitely was late to the market
here, but the set-up flow advantage is interesting.
---- ---- ---- ---- ---- ---- ----
I used Protium at the beginning of 2014, and was impressed with fast
run times to partition across the 4 FPGAs. Protium also handled some
messy, cascaded clock-gating that brought HAPS to its knees.
---- ---- ---- ---- ---- ---- ----
Cadence showcased Palladium, highlighting a use model where it is
configured in a hybrid mode with ARM Fast Models to enable faster
OS boot and software driven verification. CSR and Nvidia spoke on
using ARM Fast Models with Palladium. Nvidia even used the ARMv8
architecture.
Consequently, ARM presented its evaluation of Palladium at their
recent ARM TechCon -- the bottom line was booting an OS such as
Linux or Android goes from hours (on an emulator) to minutes (on
the hybrid), starting hardware/software debugging or running
software-driven tests much faster.
---- ---- ---- ---- ---- ---- ----
Synopsys's ZeBu Server3. New hardware based on Xilinx-Virtex7.
3X capacity as well as 3X performance versus ZeBu-Server1.
But ZeBu's long setup and slow compilation times persist. Despite
some progress in debug, I still believe that Veloce and Palladium
outperform ZeBu-Server in this critical area.
Synopsys marketing is putting emphasis on the integration of Zebu
into its virtual prototyping, RTL simulation, formal analysis,
and HAPS FPGA prototyping.
ZeBu-Server3 continues to offset Palladium-XP2 and Veloce2 in terms
of the smallest dimensions and lightest weight, as well as lowest
power consumption. The somewhat more expensive Virtex7 versus the
custom chips used in Palladium/Veloce largely offsets the cost of
designing custom silicon and is a faster path to HW updates.
---- ---- ---- ---- ---- ---- ----
We go to DAC to haggle pricing with Mike Dini for his FPGA boards.
---- ---- ---- ---- ---- ---- ----
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