( DAC'14 Item 3 ) ----------------------------------------------- [12/04/14]
Subject: Calypto Catapult beats Cadence Forte/C2S for #3 tool at DAC'14
BEGRUDGING RESPECT: Yes, the C++ designer fanboys loved Big Name Google
endorsing C-based HW design, but the biggest kudos unexpectedly came from
two of Catapult's direct rivals:
"Most wow? Sanjiv got Google to speak for his tools at DAC."
"I know you don't want EDA vendor comments, John, but the fact
that Calypto snared Google impressed me the most."
Naturally the two unnamed competitors also privately added disclaimers that
"If asked, I did not say this."
For pure tech talk, two users liked the SLEC integration and one doubted
Catapult's floating point abilities.
And one FPGA engineer even asked: "Does Mentor still support Handel-C?"
HEADS OR TAILS?: On the Cadence Forte Cynthesizer vs. Cadence C-to-Silicon
front (since CDNS acquired Forte just 4 months before DAC'14) there was
still one big C user question left over from ESNUG 537 #3:
"Do you know if Cadence has decided which C tool they're going to
kill and which they're going to promote, John?"
Which even to this day the Cadence C folks have not 100% fully answered yet.
Not one mention of the SNPS Synfora Synphony C Compiler at DAC this year.
SURVEY QUESTION #1:
"What were the 3 or 4 most INTERESTING specific EDA tools
you saw at DAC this year? WHY did they interest you?"
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The Google presentation about VP9 being designed with Catapult
C-to-Verilog-RTL was the most interesting thing.
Google is a software company designing hardware. Regular software
guys writing C code that was converted to hardware. I was very
impressed with how much they were doing. They had written a lot
of code, and they did it quickly.
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How the $*#% did those %$&(ers get Google on stage??!!
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WTF? When was the last time you saw Google endorse anything EDA?
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Google's VP8/9 project:
- Development time using SystemC/C++ is 50% less than RTL. It took
6 months (including training and learning) vs 1 year for RTL flow.
- Area and timing results comparable to RTL design.
- C-coding was much more compact. 69K C lines vs 300K RLT lines.
- C++ simulation run time is ~50X faster than RTL.
---- ---- ---- ---- ---- ---- ----
I attended the Calypto Catapult LP seminar at DAC. I like that
Catapult can make power trade-offs above RTL level. I am also
interested in Google VP9 synthesis with Catapult.
---- ---- ---- ---- ---- ---- ----
Google Catapult HLS presentation -
Implementing video encoding IP in HW. It was a Finnish company
that Google bought. Maybe a smaller company can take more risks
than Google can.
It was interesting that they were using Catapult HLS and were happy
with it. I think it took them a while to figure out. Can they
share the lessons they learned? You must go through the same pain
yourself - that was interesting.
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We'll always be an RTL synth house, but I liked the Google C stuff.
---- ---- ---- ---- ---- ---- ----
Catapult Google.
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Calypto Catapult
My scope is limited to Calypto's DAC presentation, since I am not
a user currently.
Attended the HLS session and came back impressed. Felt that design
with C is the way to go for at least portions of our design that is
algorithmic. Working with C code at that abstraction layer for design
and verification clearly is a faster.
Calypto has been working in this field for quite some time and the
ability to explore different architectures -- area vs performance
is a stand out. A good enthusiastic team.
Wondered why Wally let Calypto go out of Mentor Umbrella. Although
at one time it was niche, but now appears to be mainstream. With
Forte under Cadence Umbrella, and Calypto's sole focus is C/SystemC
based design, would be far more comfortable working with Calypto.
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I was not positively impressed by the Google/Calpto presentations.
The stand was very small and extremely noisy. The presenters did
not have a microphone (at least during the first day).
- Google presentation was lacking a lot of details and it seemed
to me very approximate.
- The improvements Google got - with respect to RTL design - were
modest because of, I assume, the lack of knowledge of HLS in
that Google group.
- I was surprised that the Google guy did not know at all about the
Calypto Sequiential Equivalence Checker (SLEC). They used, in my
understanding, GDB or console printing for verifying the correct
behavior of their design in SystemC/C++.
- Calypto presentation was better. Although Catapult C is behind
Forte and C2S in terms of QoR (this is my gut feeling). If they
originally did not support SystemC, now they are trying to filling
the gap with the competitors.
I am wondering if Calypto's C/C++-oriented (serial code) engine is
really able to be extended so easily to SystemC (concurrent code).
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MENT SLEC
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Our group says C is B.S. But I like Catapult & SLEC if we did C.
---- ---- ---- ---- ---- ---- ----
We have the traditional Design Compiler synthesis folks. Catapult
would be a hard sell to users here because it would require a serious
methodology change, hesitant to embrace new technologies.
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Although Catapult is suitable for algorithm implementation, at least
in DAC, their info on handling floating point arithmetic was a bit
sketchy.
Calypto did say that the user can specify the number of bits for
exponent, mantissa etc. -- but could not answer on applying bias.
Also they did not answer on support to IEEE 754 half-float directly.
In that respect, was a little disappointed.
Perhaps I am not a customer yet and hence the level of support was
minimal or the Application Experts on it were not present at DAC.
---- ---- ---- ---- ---- ---- ----
Asked Brett which Cadence/Forte tool was going to live.
He answered: "Both".
---- ---- ---- ---- ---- ---- ----
Cynthesizer. We have too much invested in it.
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Forte
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We do FPGAs. Does Mentor still support Handel-C?
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Related Articles
Cadence to acquire Forte Cynthesizer at rumored fire sale price
Calypto Catapult HLS trounces Forte, C-to-S, and SNPS at DAC'13
Verilog RTL, SystemC, sign-off, Catapult, middleware, AutoESL
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