( DAC'14 Item 7 ) ----------------------------------------------- [12/18/14]
Subject: Atrenta SpyGlass CDC and BugScope, plus CDNS JasperGold vs. IFV
KATHRYN SCORES!: The big news this year in formal was that Cadence bought
out Jasper-DA for a whopping $170 M - $24 M == $146 M net cash -- thus making
Kathryn Kranen the richest women in EDA.
which has inspired many EDA R&D folks to realize: "Wow! I guess you can
still make big money if you're in the right EDA start-up after all!"
 
ANGRY CLOCKS: On the tech side, quite a few engineers at DAC'14 cited CDC
issues as a problem and Atrenta SpyGlass CDC specifically. Two referenced
something new and related in SpyGlass: Reset Domain Crossings. Huh?
For Jasper users, there were concerns over the popular JasperGold Apps
being discontinued by CDNS mgmt (in favor of IVF).
One weird side note: in prior years users gushed about Atrenta BugScope.
(See DAC'13 #2, DAC'12 #5, DAC'11 #2, DAC'10 #1) This year, not so much.
And although Zocalo Zazz and SNPS Verdi got user mentions, I have no idea
why not even one engineer cited Real Intent as a Best of DAC tool this year.
SURVEY QUESTION #1:
"What were the 3 or 4 most INTERESTING specific EDA tools
you saw at DAC this year? WHY did they interest you?"
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Found "Functional CDC" verification from Atrenta useful for our
designs. Something we were looking for sometime now.
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SpyGlass CDC for asynchronous clock crossings.
We tried formal based CDC functional verification in the past
from Synopsys and Cadence, but our designs were too complex.
This new tool might work. We'll see.
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I am RTL designer who writes scripts/flows for other RTL designers
to use.
The most interesting for me this year is that the RTL verification
technology is finally converging.
- Ausdia is using their engine to do CDC.
- Jasper is using the core engine to do low power verification.
- It seems like Atrenta Spyglass CDC finally reads in SVA and
UPF to close the formal CDC verification loop.
It seems like Spyglass is closer to "RTL signoff" than any other
company because their engine is more integrated for DFT, lint, CDC
and Power analysis, but Atrenta still needs to make all of their
technologies more integrated to provide true RTL Signoff.
---- ---- ---- ---- ---- ---- ----
We had SpyGlass CDC find all our FIFOs and analyze the crossings
properly where other tools could not.
We also have run SpyGlass through a few of our FPGA designs to
look at their FPGA flow. It addressed FPGA library and IP issues
other formal have not.
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My company looked at BugScope a few years ago and liked the results
but didn't have the staffing to use it. I stopped in the Atrenta
booth to see if there was anything new and was pleased to see that
there are now several automated use models.
One of these is aimed at verifying that your blocks/IPs are hooked
up right, that they're being used as intended, that all the right
modes and combinations of modes have been verified, etc. Problems
in these areas can be hard to detect, or if you do detect them can
be hard to trace to the root cause.
BugScope was the only presentation I saw that addresses these specific
problems (block-to-block and block-to-system interaction) and it claims
to do it automatically. (No additional models or test creation and no
manual effort.) Atrenta says this flow (MARS) works for emulation in
addition to simulation.
To someone who has spent weeks trying to root cause failed tests, a
tool that can point directly to the problem sounds very interesting.
---- ---- ---- ---- ---- ---- ----
We are closely watching tools to improve our functional coverage
and efficiency of logic verification. Atrenta BugScope and
Cadence's JasperGold are on our radar.
SpyGlass CDC looks interesting this year, too.
---- ---- ---- ---- ---- ---- ----
SpyGlass CDC. Useful because:
- easy setup
- auto extract clock domain information from RTL itself.
- uses existing SDC constraints to extract clock domains.
- recognizes a range of synchronization techniques and
results with very low noise.
- user friendly debug environment. Combo of spreadsheet
and color coded schematics. Makes debug very easy.
On some recent projects, it found CDC issues:
- Unsynced paths that should have been synchronized
- Convergence of synchronized paths
- Glitchy logic in the fanin of synchronizers
Plus some Reset Synchronization issues that we missed.
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Atrenta Functional CDC.
We have been focusing on structural analysis for now. However,
we do understand the need for Functional CDC flow. It does both
formal based and simulation based technologies.
Formal Coverage that Atrenta provides seems to be unique.
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Atrenta talked about a Hierarchical SoC flow at DAC. It looked
interesting. Does divide-and-conquer to CDC verification; IP
owners ensure that IPs are CDC clean and then chip team can
verify asynchronous domain crossings among various IPs.
We plan to explore it in the near future.
---- ---- ---- ---- ---- ---- ----
SpyGlass CDC for verification of Clock Domain Crossings.
Tests correct sync of reset signals (Reset Domain Crossings).
---- ---- ---- ---- ---- ---- ----
Atrenta BugScope
Formal tools, Cadence IFV and Jasper
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JasperGold Structural Property Synthesis and X-Propagation Apps
Both interested me. They seem to be easy to use and are a low
barrier-of-entry way to get non-verification design people to check
their designs for simple oversights that cause the verification
folks debugging grief.
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Most interesting tools:
- It is not really a tool, but more a feature. The proof
core from Jasper is very interesting.
- Atrenta Spyglass Advanced Lint. It's using formal to
extend static analysis.
- Zazz from Zocalo has made good progress toward being a
mature tool.
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JasperGold: Security Path Verification App
We hope they don't discontinue it. It's key to our chips.
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Big fan of Jasper X-Prop App. Hope it's still around next year.
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JasperGold Apps. Formal for dummies. Good stuff.
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JasperGold or IVF
It'll be interesting to see which tool Charlie eliminates.
---- ---- ---- ---- ---- ---- ----
WHAT?!! I was told by Kathryn Kranen after the Jasper acquisition
that she would be staying on with Cadence. :)
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Synopsys plans to keep Verdi open and license it.
I cannot tell if that is really a lie, but it feels like one.
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Related Articles
Jasper case study on formally verifying secure on-chip datapaths
Jasper SEC & Datapath versus Atrenta BugScope were #2 at DAC'13
The secret story of Kathryn being EDAC Chair and saving history
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