( DAC'16 Item 7 ) ----------------------------------------------- [05/05/17]
Subject: CDNS Innovus/Voltus, Apache Redhawk, ICC/ICC2, MENT Nitro-SoC
UNEXPECTED INNOVUS/VOLTUS ANSWERS: When I do these "best tool of DAC" surveys
the answers in the PnR space are almost always something like ICC/ICC2 vs.
Innovus vs. Olympus/Nitro-SoC vs. Atoptech type user comments.
This year was different.
This year it was users talking about Innovus with Voltus, or Innovus with
Voltus and Tempus. Huh?
In a kind of rushed launch at DAC'16, Apache/Ansys had prematurely announced
their Big Data multi-CPU SeaHawk IR-drop tool. The problem was SeaHawk has
accuracy & repeatability issues.
Sawicki: "I've heard some things in terms of power, in terms of one
solution, where if you do a different number of CPU's you get
a different answer for nodal voltage. (See ESNUG 561 #1)
That's not good. It's worse than inaccurate, inaccurate is
kind of eh, compared to what? But inconsistent sucks."
- from Joe Sawicki on the DAC'16 Troublemakers Panel
And to make a bad situation worse, this puts John "Jolly" Lee's R&D staff in
a tug-of-war between trying to maintain an elderly declining RedHawk or
to beef up their newer next-gen SeaHawk.
And to make a bad situation even worser, Aniridh's CDNS sales army has been
in a full frontal assault against Apache/Ansys by chatting up the advantages
of getting IR-drop closed inside an Innovus PnR flow.
(click to enlarge pic)
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That's 93% fewer victims. And 26% less IR-peak. All within Innovus PnR.
Sexy stuff for chip designers doing 16/14/10/7nm. Bad news for "Jolly".
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PRIMETIME STILL KICKS ASS: Yea, Anirudh has been trying to make inroads
against Aart's Primetime monopoly. He's even claiming 250+ tapeouts
with Tempus -- but that's against a 20 year PrimeTime history of easily
10,000 tapeouts or more. "Hey, you gotta start somewhere!" The Tempus
users may really like that it's super tight with Innovus, but they're NOT
abandoning Primetime in droves (yet).
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MENT OLYMPUS/NITRO-SOC: Yes, the "big dog" PnR battle is between Innovus
and ICC/ICC2 -- but judging from the user comments, Wally's Nitro-SoC PnR is
still representing well(ish), too. I see MENT as the "little dog" in the
digital PnR wars, small and determined. Not a threat to either Aart nor
Anirudh -- but they do get their small piece of the PnR pie.
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AND ATOPTECH IS DEAD: or at least that's what the DAC attendees thought.
It's an olde story in EDA. A brutal lawsuit from a large competitor kills
off a small start-up. Just ask Nassda, Extreme-DA, and now ATOP...
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QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
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CADENCE INNOVUS & VOLTUS
Cadence Innovus
We've been using Cadence Innovus P&R with CTS for a over year. We were
an early partner.
Innovus takes you from a gate level netlist to a timing-closed design,
and Cadence went for more parallelism it. We do large-scale designs and
wanted the improved runtime and capacity.
- We found that implementing 2-3 million instances through P&R
now only takes 12-24 hours, where it used to take 2-3 days.
- This runtime includes analysis, floor planning changes, and
iterations. Once we get into 24 hour turnaround, that meets
our needs.
- We don't tend to run blocks larger than 2-3 Million gates as it's
harder to manage boundaries.
P&R has made a lot of progress over the last 10 years. In 2006, we
were running 1 million instance blocks. We spent lots of time on ECOs,
routing gaps, and hard timing optimization. Most of these problems
are now solved on the Innovus side -- but it was harder for us to spot
obvious gaps during optimization.
Now Innovus just runs, closes timing, and we move on.
Cadence seems to be investing in this area more than Synopsys is in
ICC/ICC2 (and in EDA tools in general). My impression is that Cadence
continues to see EDA as a worthwhile to invest in, while Synopsys is
diversifying more into non-EDA SW security areas.
Cadence is also building out a full implementation flow for Innovus,
Tempus, and Voltus. They are moving toward common user interface, a
common code base, and reuse of the engines.
There seems to be lots of industry interest in using Voltus. Folks are
not very happy with RedHawk since Ansys' acquisition of Apache. The
Innovus/Voltus integration is good, including lots of consistency in the
interfaces. However, Voltus is not yet mature as a product. Cadence
is still catching up in supporting all the interest. For example, folks
have their own power sign off, and their own IR-drop sign off. Unlike
a Tempus/STA signoff, a power signoff requires much more development.
Cadence tools in general originally came from a bunch of acquisitions,
so there used to be an issue of diff databases, creating data exchange
and constraints issues. For example SDC might annotate in one tool but
not the other. These issues are now gone, after the focused effort
over the last 4-5 years. You now get timing consistency, and the CDNS
tools all see the same critical path.
We'd absolutely recommend it.
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Cadence Innovus
I attended update presentations at DAC with Cadence Innovus P&R tool and
we're also hands-on users of it ourselves.
It feels like Innovus is gaining share in the market against products
like Synopsys ICC/ICC2.
1. Innovus' biggest claim-to-fame is runtime and high capacity with
reasonable runtime. To benchmark:
- We used Innovus on our ARM core design.
- We ran 1.2M instances.
- We ran it across 16 CPUs, and saw 25% to 50% performance speed
up vs Encounter. (The larger designers sped up more.)
- Our PPA quality was maintained.
2. Each of Innovus' optimization steps has more multi-threading over
Encounter. It uses compute resources more efficiently. Innovus'
ECO capability has also improved. Our total implementation time
for the full Innovus flow with timing reports, clocks inserted,
power reduction and final detailed execution was:
- now 3 days with Innovus
- used to take us 7 days with Encounter.
We got this full flow speed up, even when using Synopsys Primetime.
CSNS claims you can get more benefits with theit more deeply
integrated Tempus -- i.e. an ECO flow with sign off timing -- but
we didn't try it.
3. Innovus supports multi-mode, multi-corner timing set-ups.
- We could define all of our scenarios for the tool up front and
enable them at different parts of the design flow. For example,
for sign off, run all corners; but for implementation only a
subset of corners.
- You can have an environment where block size is only 1M, and
still run all scenarios.
Cadence discussed enhancements to Innovus GigaPlace and GigaOptat DAC.
This is the "heavy lifting" optimized placement part done early in the
PnR flow. The placement must be done right for your design to work
and Cadence is investing lots of R&D there.
One example is that you used to be able to abut all the cells in the
library. But at 10nm you must leave a space between certain cells,
while others can still be abutted. GigaPlace understands these foundry
DRC cell-based rules. I.e. it understands that some cells don't place
well with others and does the right thing.
We used Innovus at 10nm and it avoided that kind of violations that
could not simply be fixed with just metal movements later. P&R tools
must comprehend this. In fact, that was a key driver for us move to
Innovus from Encounter.
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Innovus seems to have maturity now.
The key players (TSMC, Samsung, GF, ICF) have certified it down to 7nm.
Even saw a presentation on a 5nm test chip by IMEC that was done with
Innovus. They are really driving the curve.
I heard that QCOM, Nvidia, Marvell, HiSilicon, and MediaTek are some
of the more recent adopters.
For EMIR signoff Voltus is taking marketshare. RedHawk has a hard time.
I believe that Ansys rushed their SeaHawk release -- this leaves them
with two separate products and a great opportunity that Cadence is
exploiting to grow. Cadence has paid attention to ease of use by
adding a VCD visual display analyser (for example) to visualise high
resistive paths in the GUI. Voltus is fast, too.
Voltus still has growing pains and bugs to iron out. For example,
it has little support for hierarchy. Also the Voltus save/restore
was buggy and core dumped.
That said it's a good product. Watch out Ansys!
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Innovus -- I see massive traction in the 16nm market market adopting it.
Anirudh was smart to integrate his Tempus and Voltus to his PnR. That
moved our management over towards Cadence.
I wonder if Innovus will also be the next gen tool for 10nm and 7nm.
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I've used Cadence Innovus with Tempus for my last two projects.
I'm currently working on an ARM core. My overall assessment:
- You can be productive with Innovus without a lot of past PnR
experience. The flow/methodology can give you "tapeout quality:
for your design with a lot of automation, and without a steep
learning curve. Anirudh has managed to make it easier to build
quality designs for a non-expert, so you can send your designs
to less sophisticated design centers.
- Innovus is also powerful for a physical design expert. You can
drive it harder -- it does, of course, take some time to know
which knobs to use in this mode.
Innovus speed is very fast compared to the P&R tools I used a couple of
years ago -- AtopTech and Magma Talus. I can now run at least 2X the
size of a design overnight as I did previously. To do this we took
advantage of Innovus 16 CPU parallel distribution.
- For 2-3M instances, in an overnight Innovus run, we can get
simple placement.
- For 1M instances, in an overnight Innovus run, we can get:
placement optimization, Clock Tree Synthesis optimism (CTS)
and routing optimization.
From a capacity standpoint, the largest block we've tried successfully
was 4M instances.
Innovus is also strong for its full entire flow. We used to use
Synopsys Primetime for our timing sign-off, and it took us a lot longer
due to correlation issues, then did a number of shadow runs with Tempus.
Once we made sure the accuracy was okay, we switched to doing timing
MCMM sign-off with Tempus. Going through PnR is much faster now.
- We go through timing sign off with restricted corners (and
usually this is the bottleneck) as we cannot afford to look at
all modes and all operating corners during optimization.
- When we setting up Innovus for timing closure, we get very close
right away. Even so, some corners may not be covered -- this is
where the Innovus/Tempus full sign-off integration makes a big
difference. The timing tool and back annotation are completely
compatible and tightly correlated.
- We do a lot of timing ECOs. Once Innovus is done, we go back and
forth to close the loop to resolve the timing violations. We try
to minimize over-design by avoiding extra margin during timing
optimization and close only the viloations required by signoff
timer.
We still use Ansys Redhawk for gate-level power analysis, but we've
heard good things about Voltus, and are looking at it now. We are once
again doing shadow runs to verify Voltus' sign-off accuracy before we
decide to switch over.
Innovus gives us "tapeout quality QoR" quickly. Innovus also allows
us to push hard for performance or area when desired.
Innovus seems to doing much better in the market in last 2 years. In
the past, I used to hear bad opinions of Cadence PnR (from other people,
since I wasn't a user then.)
That has changed under Anirudh. Based on my experience over these
last 2 projects, I'd definitely recommend Innovus.
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We are using Cadence Innovus, Tempus, and Voltus. We've seen some
capacity improvements in Innovus as compared with the old Cadence EDI
a couple of years ago. We have a different generation of blocks now
so I can't make a direct comparison (16nm vs. 28nm), but we would have
had to split these 10nm blocks up to get them through EDI.
GigaPlace and GigaOpt are key technologies within Innovus. We've seen
better QoR with these. GigaPlace is their timing closure aware placer,
and GigaOpt is used throughout for timing closure.
We use Innovus for two major modes: set-up timing, and hold timing,
where we add additional view constraints -- more and more info. We
use 4 CPUs for set-up timing mode, and 8 CPUs for hold timing mode.
The largest blocks that we've run through Innovus are 1M-2M instances,
and highly complicated in Ghz terms and phases of clock frequencies.
- At 16nm with messy timing, we are pushing against the limits and
causing Innovus to work harder. It takes a week to go through
entire flow, including Tempus and Voltus.
- We can get the smaller, less timing compilcated blocks through
the full flow in 2-3 days.
Innovus has signoff and ECO integration with Tempus and Voltus. You
can call Tempus from within Innovus, but we use Tempus standalone.
Tempus ECO allows you to do last mile timing and power and area,
which we use.
We are trying 7nm, which is working on the bleeding edge, and Anirudh's
R&D has been very responsive about fixing the bugs we find.
We also use Voltus standalone. Cadence's Voltus integration is less
mature; we would like to see more Dynamic IR-aware optimization, and
Cadence is starting work on that.
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Innovus. Cadence discussed better TAT, performance scalability, ability
to handle very large blocks, signoff and ECO Integration with Tempus and
Voltus.
Each of these features is significant, and it all has to work together.
The high capacity with the integrations (signoff & ECO) represent a leap
forward to any other design flow. The industry is full of stories where
the design flow has made the difference between successful designs and
designs which were either never built or were late to the market.
Innovus is one of the great products in EDA history. Anirudh recruited
a very strong team from many places, including many key developers and
product owners from Magma, to add to Cadence's existing resources. He
also re-architected and re-architected wherever needed.
The result is something of a "super-tool" with all critical features for
10nm design of the other implementation tools in the industry, with
better integration and better runtime/capacity.
If Cadence's competitors don't make similar investments (and maybe if
they do), Innovus is well positioned to dominate physical implementation
now & in the years to come.
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Innovus. Their Imec 5nm DAC presentation was good. Not as detailed
as what you had, John. (See ESNUG 554 #3.)
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We're leaning Innovus for our 7nm chip.
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ANSYS/APACHE SEAHAWK & REDHAWK
The new tool Ansys tool, Seahawk, with elastic computing. Impressive
computation time and data management.
We are interested in benchmarking it as soon as possible on our design
flow and on our compute farm.
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We're staying Redhawk for now.
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MENTOR NITRO-SOC
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Nitro throughput of 2M inst in 24 hours for PnR caught my attention.
Mentor claims that Nitro is a complete rewrite of all the key engines
including placer, optimizer, router and the database. They have also
completely overhauled the flow scripts and used multi-processing and
threading.
Dynamic power-aware flow and 10% additional power reduction vs ICC2,
area and die size down 10% using abutted floorplanning and area
recovery. Direct interface to Calibre -- run Calibre DRC/DP/DFM
checks and automatically fix violations.
ST and Nvidia presented. Overall a very interesting tool
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Mentor's Nitro P&R system was interesting. Their runtime claims are
5 time faster compared to their previous generation with a throughput
of 2 million instances in 24 hours. Support for 10nm and integration
with Calibre, power analysis and optimization delivering 10% less
power, especially for FinFET nodes.
Their channel-less hierarchical floorplanning methodology supposedly
cuts down die size and area to the tune of 10% compared to the channel
based flows. Nvidia presented on the Nitro hierarchical floorplanning
and how it helped reduce their floorplanning cycles.
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Nitro-SoC is faster this year.
The speedup is apparently from the complete rewrite of all the engines
and also from utilizing hardware for parallelization. They enhanced the
interface to Calibre to handle multi patterning rule fixing for smaller
nodes (14/10nm) which should reduce the physical verification cycles.
We typically go through 4-5 iterations for DRC clean-up and this should
help drop it down significantly.
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SYNOPSYS ICC/ICC2 -- oops! got no user comments!
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ATOPTECH
Don't want to be negative but the Atoptech booth was empty at DAC.
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We're looking at Innovus to replace ICC.
We disqualified Atoptech because of the lawsuit issues. Too messy.
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I don't think Atoptech will be around by next DAC.
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ATOP booth == ghost town
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