( DAC'16 Item 9 ) ----------------------------------------------- [05/19/17]
Subject: Calypto PowerPro -- but no Ansys PowerArtist nor Synopsys Spyglass
AND THEN THERE WAS ONE: Five years ago there was a massive threeway dog
fight in the RTL power optimization niche between Apache/Ansys PowerArtist
(the oldest tool in that space), Atrenta Spyglass Power (the market leader
at one time), and Calypto PowerPro (the "me, too" tool at the time.)
It was the big #1 EDA tool drama of the times at the beginning of DAC'12
with Atrenta vs. Apache vs. Calypto battle in RTL power optimization. But then
after DAC'12, Apache PowerArtist started slipping...
SpyGlass Power, PowerPro RTL, with some PowerArtist users at DAC'12
http://www.deepchip.com/items/dac12-01.html
And then by DAC'13, PowerPro moved to #1, SpyGlass Power to #2, while ANSS
PowerArtist completely fell off the radar as far as users were concerned:
It was just Calypto PowerPro vs. Atrenta Spyglass Power at DAC'13
http://www.deepchip.com/items/dac13-03.html
And PowerArtist again stayed missing after DAC'14 of last year:
Calypto PowerPro, Atrenta SpyGlass Power, but no Apache PowerArtist
http://www.deepchip.com/items/dac14-09.html
But then by DAC'15, Ansys/Apache PowerArtist made an unexpected surprise
comeback -- but then SpyGlass Power disappeared after Aart had bought out
Atrenta at that very DAC'15 -- creating all sorts of customer doubt.
Calypto PowerPro, Apache PowerArtist, but no Atrenta SpyGlass Power
http://www.deepchip.com/items/dac15-07.html
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DISTRACTED RIVALS: Now the street rumors back then were lots of users were
furious that Aart had raised the prices of all *his* Atrenta tools (some by
as much as 3X the price!) -- which might explain why not one user listed
Spyglass Power as a "Best of" tool for 2016...
And that Ansys/Apache (the owner of PowerArtist) was putting all its efforts
into getting John "Jolly" Lee's brand spanking new Big Data SeaHawk IR-drop
off the ground -- meaning poor olde PowerArtist was ignored -- which might
explain why not one user listed PowerArtist as a "Best of" tool for 2016...
Yup. You got that right. Where it once was a threeway fight, it appears
that now only Mentor Calypto PowerPro got any "Best of" tool user mindshare
in 2016... Happy Wally. Sorry Aart. Sorry Jolly.
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ON THE TECH SIDE: PowerPro estimates at the RTL come to within ~15% of
the final placed-gate dynamic (switching) & static (leakage) power numbers.
PnR can be ICC/ICC2/Innovus/Nitro-SoC as long they do SPEF tuning. (MENT
uses PT-PX and Voltus as golden; but distrusts any PowerArtist numbers.)
Their SLEC equivalency checking is its differentiator. When it re-writes
the RTL code to optimize power, PowerPro will then do a formal to check vs.
original. Neither Atrenta Spyglass nor Ansys PowerArtist can do this.
Their users have to do this procedure manually.
NEW THIS YEAR: Calypto PowerPro ECO flow and Activity Audit.
With the PowerPro ECO flow you can now change your (non-CG optimized) source
RTL and generate optimized RTL just for the changed section of your RTL code
to minimize the impact of that change.
PowerPro Activity Audit analyzes your switching activity for obvious issues
like: nets with no switching, missing modules, but it will also help with
your RTL-to-gate switching activity mapping issues.
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QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
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MENTOR CALYPTO POWERPRO
Mentor Calypto PowerPro
I've been following RTL power analysis tools for years.
I saw Mentor PowerPro at DAC. Below are the features I thought were
noteworthy based on that discussion. (We have not used or evaluated
it.)
1. Mentor PowerPro power analysis appeared to have a good correlation
- Power estimation must correlate with the gate level netlist,
and with silicon.
- RTL Power Estimation was within 10-15% of was what reported,
and is what I'm is expecting.
2. Good exploration support
- For example, if we explore multiple micro-architectures, and
one is more power efficient, good that result will remain in
silicon.
3. PowerPro's power reduction, e.g. for logic, clock and memory
optimization. How much power savings do they get following the flow?
- Mentor says ~10%. You can get 5 to 25%, depending on the block.
More if the block was power agnostic, and less if it was already
power optimized.
4. The equivalency checking is powerful. This is a differentiator for
Mentor
- When you automatically re-write the RTL code to optimize power,
PowerPro will then do a formal to check vs original.
- Other power tools do not support this and designers have to do
this procedure manually.
5. Deep sequential analysis
- You get machine generated expressions surgically inserted into
code. As a designer, you stay at the top level that you
understand when you make your design changes to reduce power.
With sequential analysis you can explore deeper for better results.
- It comes down to confidence. Having sequential analysis offers
built-in confidence, so designers are more willing to implement
the changes. We had this issue with another tool, where we got
suggest and didn't implement.
- Mentor claims they do deeper sequential analysis than the other
vendors.
This could be true, in the sense that more optimization suggestions are
going to end in the final RTL code due to inbuilt equivalence checking,
I just don't have any direct evidence.
6. PowerPro Designer's one positive side effects is you can quickly
run iterations to try out different flavors of your design,
including microarchitectures, libraries, or voltages.
- The tool brings in a model and annotates it for libraries.
- PowerPro inserts parasitics, so when you do what if analysis,
you can change the inputs or parameters, and do quick
iterations during design.
- You can do this same thing with gate level power analysis. But
it is more time consuming and takes more effort than at the RTL
level
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Mentor Calypto PowerPro
We're interested in finding out more about PowerPro. Its micro-
architectural power reduction looked interesting, e.g.power-gating at
the block level, and being able to identify the higher level enables.
PowerPro's automated equivalency checking for the power reductions
design changes is also interesting. The deep sequential analysis is
attractive if it works in a way that produces practical results.
Power analysis accuracy is important, and we want to assess it.
- If the RTL power reduction design changes are done automatically,
then less precision is needed.
- For RTL changes done manually, e.g. the changes PowerPro
suggests during 'guided power optimization' makes sense in general.
e.g. if the tool says it saves 10 microwatts, but really only
saves 4 uw, we may still do the design change anyway.
This is where the priority order becomes important to get right, so we
only rewrite RTL, for anything saving more than 10 uw for example.
- It's also important to look at accuracy by category: i.e.
combinational, register, memory, clock power, etc. Saying that
the total dynamic power is within 15% isn't necessarily that
helpful if each category can be +-50%.
In general, you need macro placer to get really accurate. It's better
to have SPEF vs. not having it; however even parasitic prediction needs
placement information for accuracy. With some manual tuning, you can
get the accuracy.
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Calypto PowerPro RTL Low Power
We integrated Mentor PowerPro-CG and SLEC into our SNPS ICC flow for
automatic power savings.
With conservative settings, we are seeing around a 5% (post-layout)
dynamic power reduction on our active use-cases.
One of the best ROI's of the power reduction techniques we use.
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Two new Mentor PowerPro features perked my interest: ECO flow and
Activity Audit.
With ECO flow you can now change your (non CG optimized) source RTL and
generate optimized RTL just for the changed area of the code to minimize
the impact of the change.
Activity Audit will analyze your switching activity to point to obvious
issues like: nets with no switching, missing modules, but will also help
with RTL to gate switching activity mapping issues.
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Calypto PowerPro
In general, Mentor PowerPro sounded useful, both:
- The design guidance
- Not having to leave PowerPro to test the design changes to reduce
RTL power.
Mentor's power analysis accuracy claims sound reasonable:
- 15% accuracy at RTL
- 1-2% accuracy for gate level.
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Mentor PowerPro. It's most noteworthy features:
- Automated guidance for RTL power reduction.
- Embedded formal engine to automatically identify long paths where
you could do clock-gating to save power.
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We use Calypto PowerPro during RTL design. We do as much power reduction
as possible before the final verification milestone, as we are reluctant
to make code changes once its fully verified.
For most derivative designs, 90% of our design come from 3rd party
purchased IP coming or legacy IP. The scope of power reduction in this
context is primarily around any IP modifications and SOC glue logic
being done for the project. As we modify the IP or create a complex
subsystem from it, we need to make sure that our new code doesn't mess
up our power.
PowerPro does sequential analysis to find opportunities for additional
clock gating very well. It can find interesting clock gating cost
functions and go deeper in the sequential tree than easily feasible by
manual means by the RTL designer. The designer can review its
recommendations and incorporate the changes in his design.
Based on some dry runs we did, Mentor PowerPro was better than Apache
PowerArtist and Synopsys/Atrenta Spyglass Power tools in that order.
PowerPro:
- Presented more interesting power reduction opportunities
- Intuitive in data presentation. Easier to get the necessary
information -- was very usable.
- The PowerPro GUI was more thought through. For example, Mentor
puts CG/MG recommendations in more interesting buckets/categories.
When you run PowerPro, the tool will say these are the issues and these
are safe changes to make. You can prove it by taking their cleanly
annotated RTL and using their logical equivalency checker to check
against the unmodified RTL. This is a nice automated flow, but it's
only available if you also purchase SLEC. I have used it, and it's a
good tool, but Mentor charges a lot for it. Prudent buyers may not
purchase SLEC to save on cost because it is not absolutely critical
unless you are doing Power reduction as a post process (instead of as
an early RTL process).
PowerPro has given us early power reduction predictions showing a 12-15%
savings. Following our implementation, we typically get 5-7%
improvement for the suggested optimizations we select ... we could
possibly get more if we did more, but because we don't use SLEC, it
would be riskier to implement some of them. There is also the
designer's assessment on scope of change vs reward, because the
correlation between smaller power reduction recommendations vs what
happens in actual physical design can sometimes be a wash. This is
because:
1) There is no industry standard on synthesis algorithms, and
2) The synthesis tool vendors don't want to share their algorithms,
RTL power estimations can inherently only be so accurate. In the
meantime, I would suggest that since Mentor has its own synthesis
tool, if the PowerPro synthesis algorithm matches Mentor's
synthesis tool a 100%, Mentor can advertize exact correlation if
using their synthesis flow; however, we use Cadence backend tools,
so this would not benefit us greatly.
PowerPro was hands down the best power tool I found for early RTL power
analysis. Good GUI and good capabilities overall.
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It's still odd that Mentor Veloce uses the Ansys PowerArtist app.
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SYNOPSYS ATRENTA SPYGLASS POWER -- oops! got no user comments!
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ANSYS APACHE POWERARTIST -- oops! got no user comments!
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