( ELSE 06 Item 13 ) -------------------------------------------- [ 06/23/06 ]
Subject: Mentor Precision vs. Leonardo Spectrum
THE GOOD OLDE DAYS -- If you talk to a Mentor Precision salesman, if he's
drunk and being honest, he'll probably tell you that his biggest rival is
Synplicity and the "free" RTL synthesis tools from Xilinx and Altera. But
from what I hear from a few of the really pissed off users is that his
biggest rival is their very own Leonardo Spectrum! Those are the few
leftover diehard Leonard fans; if you read on you'll see that most of the
Mentor FPGA customers have moved on to Precision.
We started using Mentor's Precision RTL FPGA synthesis about 2 years
ago. We use it on large Virtex 2, and Virtex 2 Pro designs; mostly
datapath designs with filters FFTs, etc. We have been happy with it.
Its quality of results meets our requirements, and it has gotten more
user-friendly over time. Precision's biggest plus for us is that it
met some tight timing constraints -- 160 MHz on a 70% full Virtex-2.
We also like Precision's Synopsys Design Compiler (SDC) support.
We still have less experience with Precision than we had w/ Leonardo,
but our experience is growing.
- Steve Wakelam of Roke Manor Research Ltd.
When we used Mentor's Precision version 2005a, it was not possible to
teach it to not flatten out a specific hierarchical element. Even
worse, the logic produced did not work as designed. However using
Leonardo Spectrum for synthesis made the design work.
Guess how my eyes popped out of my head when looking at the Xilinx
timing report. I had a clock-to-output constraint of 7.5 nsec. Using
Precision, it did not meet timing, the best Xilinx could achieve was
7.9 nsec! Not changing the design but switching to Leonardo Spectrum,
all of a sudden that constraint was easily met showing 6.3 nsec!!!
Leonardo was not even constrained, all I used was an UCF for Xilinx.
This is not a slight difference, this is dramatic!
Guess which of both tools does better on inferred ROM? You get it:
Leonardo Spectrum! Why? Precision Synthesis checks the number of
address bits and (boom!!!) knows the ROM must be 2 to the power
of (address bits) deep and as wide as data is.
Leonardo is much smarter and actually seems to check the data contents
and its dependency on the address. If it finds out that a data bit is
not dependent on a specific address bit it collapses the ROM depth
yielding a huge savings.
Why are there features that the older Mentor tool has, but the glossy
new one does not have?
Which of the two tools is my tool of choice for the next designs?
Certainly not Precision Synthesis.
- [ An Anon Engineer ]
We use Precision RTL and are satisfied with it. Unfortunately we still
have to implement changes in old Xilinx 4000 series and for that we
also have to come back to a frozen version of Leonardo Spectrum. This
will become more and more of a real problem when we will have to
upgrade our old devices.
We have a very good relationship with Mentor Graphics, that allows us
to propose some enhancements to Precision. Some of them regarding RAM
initialization for example, have been implemented and we're very happy
about that. We are still expecting Mentor to add new incremental
design features to Precision RTL.
- Alain Giraudat of Thales Group
We use Mentor's Precision RTL (not the physical product). We migrated
from their Leonardo Spectrum product, and have actively used Precision
in live projects from 2003. The initial setup was reasonably quick
(~2 weeks) since Spectrum was reasonably compatible. The initial
results were disappointing, requiring several months of work by Mentor
FAEs to get frequency and area results comparable with the previous
Spectrum release.
Initially, Precision was touted to provide push-button high QoR output,
but in reality, to extract the best results required just as much
constraining and RTL style considerations as their previous Spectrum
product.
We have since used Precision on designs ranging from CPLDs to 1M+ ASIC
gate FPGA designs. The capacity seems good, and the speed seems
reasonable -- 1M+ ASIC gates/hour. The quality of results has been
variable. The 2005 versions initially produced very poor QoR for
inferred RAMs and DSP blocks, whereas 2005b release is now acceptable.
Precision's Pluses:
1. Precision's simple command line interface is good for our scripted
build process.
2. Synopsys DC (SDC) support is useful.
3. Its inference of RAMs and DSP blocks, which is now good. This is
actually Precision's biggest strength.
Precision's Minuses:
1. Stability of graphical view needs improving, as large designs seem
to cause crashes.
2. Needs more thorough customer testing between releases, as often
older designs don't work correctly with the newer tool. For
example, our move to a new front-end parser has been painful.
The 2005b release is currently broken for some Virtex4 RAM inferral
cases. Mentor should consider a database where customers can
upload designs for inclusion in their regression suite.
3. Guaranteed performance (esp. between releases) if following
published RTL style guide.
Precision features and enhancements that I would like:
1. A standalone xdb viewer would be useful. Update to allow direct
reading in of ixdb files without renaming.
2. Enhanced pragma application reporting. i.e. confirmation that it
found the pragma and is using it.
3. Better logging, such as explanations in the log as to why certain
warnings are generated - e.g. why it hasn't inserted particular
buffers
4. Prompt update of known errata/defect lists.
5. Built-in crash-back reporting. i.e. sending design database, stack
dump, etc. directly to Mentor if enabled by the user.
Overall Precision is a good tool, but experience has shown us that our
own regression testing of new tool releases is the only way to ensure
reliable results. Mentor's Software QA seems to be letting us down
recently. On the other hand Mentor's technical support/responsiveness
is second to none, for which they should be congratulated.
As for any competitive FPGA synthesis comparisons, generally we find
it is very design variable. Some designs have done markedly better
under competitors' tools and some much worse, so overall we choose
the "best" synthesis tool on a per design basis based upon the
results we get.
- [ An Anon Engineer ]
We evaluated Mentor's Precision RTL 2005b.91 according to the following
criteria:
- Clock detection for a design with multiple clocks
- Timing results with only clock constraints applied
- Identification of critical timing path
- Readability of technology view for the synthesized design
- Abundance of design constraints available
- Ease of applying constraints to the design
- Quality of user guide
We evaluated Precision on DSP algorithms, and the target device was a
Altera Stratix II (EP2S180F1020). The designs ranged from 40% to 70%
ALUT's. We compared Precision RTL 2005b.91 & Synplify Pro 7.5.1.
Our general impression was that Precision's speed was about the same as
Synplify Pro. As for quality of results, Precision did a good job of
detecting the clock paths of multiple clock designs. As a point of
reference, Synplify Pro detected 2 out 4 clock paths while Precision
detected all 4 clock paths for the same design. Additionally, with
only specifying the maximum frequency of 200 MHz and no other clock
constraints Precision was 1 MHz away from meeting timing while Synplify
Pro was 5 MHz away.
On the positive side... the best things about Precision today are:
- Detection of clock paths for a multiple clock design
- Ability to specify the I/O standard type for the interface pins
within Precision.
- Variety of constraint options available by supporting Synopsys
design constraints.
- Good window panel layout and menu flow.
- Operation for the most part is intuitive. Documentation is adequate
for learning more how the tool operates.
On the negative side...
- Our initial experience with Precision two years ago did not go very
well because the tool crashed a lot during synthesis. But Mentor
seems to have fixed this with Precision RTL 2005b.91.
Mentor still needs to improve Precision's iterative approach to timing
closure. After two iterations of changing constraints, the design
database would get corrupted to the point where the timing report did
not make sense. Our workaround for this was to store the constraints
applied to the design in a file, reload the design after deleting the
files created during synthesis, then apply the updated constraint file
for another synthesis pass. In the three DSP algorithm type designs
that we synthesized, we were able to achieve timing closer by simply
constraining each clock path of the multiple clock designs. However,
the day will come when other constraints will need to be applied in
order to close timing in an iterative constraint application approach.
The ability to define multiple I/O standards within Precision is a nice
feature. Additionally, Precision generates a Tcl script that sets up
the environment for your target FPGA place-and-route environment. On a
scale of 1 to 10, I would give Precision a 7. It seems to me that
Mentor needs to improve the way they test Precision. They are close to
having a very good product.
- [ An Anon Engineer ]
Our group is responsible for designs targeting Aerospace. My research
involves radiation effects on FPGAs and associated hardened-by-design
techniques for fault correction. In targeting an Actel device, which
is the most widely used FPGA for flight designs, we've seen that
Precision follows our hardened-by-design implementation guidelines for
aerospace better than Synplicity. In fact, sometimes Synplicity
produces logic that can be more susceptible to upsets.
- Melanie Berg of NASA Goddard
What we saw during an aggressive Xilinx Virtex-4 project 18 months ago
was that Precision was unusable and we had to use Synplify. Since then
Precision caught up significantly and today we use both in parallel.
One interesting observation we made is that Synplify does slightly
better area optimization, but is slightly more likely to lead to
routability problems later in Xilinx ISE.
- Alfred Fuchs of Siemens
Mentor Precision's performance has improved by about 3-5%, because they
added gated-clock support with RAMs and latches. Unfortunately Mentor
has not improved debugging at all. We would like them to add an
internal node observation function. Specifically, we would like Mentor
to add a function to connect an internal signal outside for debug. We
would also like them to add a function like a simple ICE that uses the
read-back function... equivalent to Synplicity Identify).
- Takahito Miura of Densotechno
We needed FPGA physical synthesis to do ASIC-to-FPGA prototyping.
We purchased Precision mostly because we have gated clocks within our
ASIC and needed gated clock conversion, and as far as we can tell
Xilinx's free synthesis doesn't have that feature.
We upgrade and resell IP from large semiconductor companies, such as the
soft version of Infineon's 16-bit C166S processor. Our customers do
FPGA prototyping so we need to also be able to synthesize to an FPGA
platform to support them.
This project was my first exposure to Precision. I took our frozen RTL
code and ran it through Precision. My understanding is that I could
have then run it through Precision P&R by simply pushing a button, but
instead I took the Precision-generated netlist and ran it through
Xilinx P&R. I did this because this was my first time using Precision,
so we only wanted to rely on part of it... especially since I already
had my own set of make files and scripts for Xilinx. For our next
project I will try Precision P&R also.
Precision pretty much worked as I expected. The only problem I had was
with the gated clock conversion, which had some unexpected behaviors at
first. I called up the Mentor hotline and found them pleasingly
responsive, but while they were working on the ticket, I ran a small
file and was able to solve the problem on my own. As it turns out, I
needed to have Precision flatten the netlist first. Actually, all the
information needed to use the feature was in the documentation, but
referencing it was difficult; Mentor could improve the documentation
for that feature.
Based on my overall initial experience with Precision, I would recommend
it to other users. It was easy to use, and it only took a couple of
hours to go through the entire flow. We worked with Xilinx and Altera
free synthesis tools before, and they are fine for small projects but
seem to be missing some of the advanced features that Precision has.
- Benedikt Schmaenk of IPextreme
I saw the Precision demo. I liked that it seems to perform physical
synthesis that ties together with the final device architecture. I
didn't like that it didn't support the Synplicity constraint file, and
seemed harder to drive than Synplicity, though haven't used it to know
for sure. I would be willing to attempt an eval of Precision, and I
believe our department is going to do one.
- [ An Anon Engineer ]
As I see it, Quartus is leading the FPGA-vendors tools (we're designing
chips in Altera, Xilinx and Actel) so Mentor's Precision RTL brings
probably less added value in the case of Altera devices, especially for
small companies with limited budgets. There is, IMO, a clear value
added for Precision with Xilinx and Actel users facing timing closure
or in general performance or design management issues.
I would certainly recommend Precision Physical for large Xilinx devices
and for Actel users.
I would recommend Precision RTL for ASIC prototyping. It has a
Constraints Verifier, and the "wizzard-driven" constraint editor is
certainly welcome. Precision RTL has a very good "understanding" of
the design and of the target FPGA. In particular, it detects complex
clocking schemes, derives contraints automatically when PLLs/DCMs are
used, and in case of internal derived clocks. Precision RTL can detect
and check for (against) clock domain crossings! Gated clocks are
automatically transformed into Clock Enable.
I personally advise to avoid gated clocks in the RTL code, but this
can come handy in cases of less well-behaved IPs or external code.
This transformation is automatic, and I would have preferred if
Precision RTL was more verbose about finding and transforming gated
clocks, but the job seems well done and the functionality respected.
- [ An Anon Engineer ]
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