( ELSE 06 Item 17 ) -------------------------------------------- [ 06/23/06 ]
Subject: Mentor Calibre DRC/LVS
FEEL THE BACKLASH! -- A little over 6 months ago I released the results of my
annual Synopsys Census and in it was the surprizing news about where DRC/LVS
users *expected* to be in the future:
Magma Mojave: ############################## 76%
Cadence PVS: ######## 21%
Synopsys Hercules: ##### 12%
Mentor Calibre: ### 8%
- from http://www.deepchip.com/items/snug05-15.html
Out of nowhere, the users said that Magma Mojave had replaced Calibre as the
future of DRC/LVS. Worst yet, Calibre was now in last place! (And a month
earlier, there was that "new" Synopsys Hercules video.) This unexpected 1-2
punch on Calibre brought out its long time users and supporters. (Duck!)
The other thing you should do is go check out the Magma Mojave section of
this census. You'll find that there's no tsunami of ex-Calibre customers
yarping about how they had just switched over to Mojave. So far, Mojave's
"threat" to Calibre has been an awful lot like the massive build up of hype
that preceeded the "Star Wars: Episode I - The Phantom Menace" movie.
People were expecting the next Luke Skywalker or Hans Solo; instead they
got stuck with Jar Jar Binks. "Monsters out there, leaking in here. Weesa
all sinking and no power. Whena yousa thinking we are in trouble?"
Thank goodness for Mentor's Calibre. Our company went to Assura after
decades of wringing all that could be wrung out of Dracula. We awaited
Assura's release with great anticipation but were met with great
disappointment. After only a few LONG years we have now gone to Calibre.
Calibre delivers the best of both worlds. It implements useful graphical
interfaces with GDS checking. Why would anyone want to check anything
other than GDS? Afterall, GDS format is what gets fractured. Why mess
with an intermediate step? Assura would often give cryptic error reports
that required a great deal of investigation and creativeness. While I
like a challenge, my manager isn't crazy about me trying to be creative
when we're trying to meet a deadline. Just get it done! Calibre allows
me to do this much more efficiently.
In addition to graphical interfaces, Calibre will give coordinates of
devices in question. This archaic but useful location method can be
especially useful with top-level or large blocks where short nets may
not show up with an interface. Calibre will also show discrepancies
from multiple approaches, i.e. a device in question will show up on a
list of incorrect nets, incorrect ports (if applicable) and/or property
errors. It also creates databases for softchecks, shorts and opens.
Both the source netlist and the extracted netlist (from layout) are a
click away for comparison in the RVE interface.
- Chad Smith of AMI Semiconductor
The thing that pushed us to Calibre was the speed. Some of the engineers
here had developed a new quick design flow in a compact process. We were
struggling with Assura (running 20+ hours). Without major tweaking,
Calibre was able to run in less then 5 hours.
- Jake Wright of AMI Semiconductor
I have been using various LVS/DRC engines since 1993. The majority
of that time has been on Mentor products -- first IC Verify, then
later onto Calibre, both early in its adoption (~1998) and especially
of late (2002 - today).
I have also had the chance to use Hercules (1999-2000 time frame),
Assura (2001-2002 time frame), and some of the older, non-hierarchial
tools such as Diva and Dracula.
The chips our group designs are usually highly hierarchial. We do
multi-channel switches, and design them from the ground up to
utilize large amounts of hierarchy. One of our more recent chips
was a 17x17mm 92 Million transistor device implemented in TSMC13.
This device had only 5 major blocks. Three of these were "analog",
being mostly based on schematics, and highly hierarchial. The other
two blocks were standard place-and-route. This design took
approximately 1 hour to run through LVS on a dual-processor Athlon.
After using all three of the major hierarchial tools, you'd have to
work really hard to make me give up Calibre. The biggest reason is
that its debugging capability is so far ahead of all the other tools
out there. I still feel that Cadence has not gotten to the level of
debugging ease that ICVerify had in 1993. Hercules was a bit better
than Cadence, but still lacked certain critical features, such as
a good short finder.
That said, there are some features of both Assura and Hercules that
I liked. I liked the derived layer browser that Assura has. When
writing custom rules, it was nice to see what layers were created.
With Mentor, I usually have to hack the rules file repeatedly. Most
users would never use this feature, but on the occasion I have had
to write rules, this would prove to be quite handy.
From Hercules, I loved the ability to permute/commute I/O signals to
blocks. We use a lot of differential logic, and sometimes the analog
designers (including myself) would get lazy and invert all inputs and
outputs. Technically, it's the same cell. With Calibre, you won't get
a good match if this is done throughout the design, unless you turn
off the hierarchy at that level.
My only other gripe with Calibre has been with the introduction of
things like fill and via insertion rules. This can cause some strange
device promotion in subcells, caused by differing implementations of via
insertion at the top level. This usually causes a false negative
(design is clean; Calibre says that there's a problem). I often have
to run final LVS flat to solve this. I haven't run Assura or Hercules
on a design node that required Via Insertion/Fill, so I don't know how
those tools compare in this regard.
I'd say that about 70% of all LVS time is spent in the debugger. The
ability to easily see the extracted netlist, as well as the schematic
makes Calibre easy to use. I have often used Calibre to help with
ECO's -- I make the netlist change I want, and let Calibre guide me
to where the offending gate is. The other feature that we use all
the time is short isolation. Since we do a lot of hand hookup, it
is quite common to short power/ground. In the days before short
isolation, I would spend hours poring over power supply rails trying
to find the short. Now, my biggest complaint is that the tool
doesn't show me ALL of the shorts at once.
On the few times I needed support, Mentor has been quite helpful. Last
summer, our LVS/DRC rule-writer was on Sabbatical, and a high-priority
request came through for a new rule. A quick call to a Calibre FAE
got me rolling in about 30 minutes, and I was able to take it from
there and get the rule out in just a few days. This new rule was not
trivial, either -- I had to check that a P+ antenna diode could not
be forward biased, and I did it only through DRC commands.
Overall, I don't think that there's a better tool currently out there.
Calibre gets me to tapeout in about half the time I would spend in any
other tool.
- Ron Talaga of Vitesse Semiconductor
I began using Calibre LVS/PEX tool recently for SRAM extraction. We
have been using the hierarchical extraction capability to create full
RC extracted DSPFs for our drop-in SRAMs (up to 650,000 bits) in our
150 nm process. We have been successful in simulating the resulting
DSPF in HSIM. The flow seems promising for addressing larger SRAM
designs as well.
- [ An Anon Engineer ]
We're still pleased with the results Calibre has at 0.18 um. We're not
yet into the 90 nm business, but it's up to Mentor to prove that they
are still better with Calibre than Synopsys or Magma.
- [ An Anon Engineer ]
One thing I like about Calibre DRC is that I have ability to verify and
record all Design Rule Waivers. I can reload this waived file during
iteration of refining and tweaking design at last stage, the waived
errors are all marked already. It saves huge time when I have over a
thousand markers in a design deviating from the foundry Design Rule.
- Michelle Lee of Guidant Corp
Calibre Performance
+ Calibre LVS and DRC is still the industry leader for cell
level to full-chip backend verification.
+ Calibre xRC is essential for the design process as it can
provide parasitic data in various formats that can used by
simulation tools (ie., spice, DSPF, SPEF).
+ The availability to run on 64-bit linux multi-processor
machines allows for reasonable full-chip debug.
Calibre Debug Capability (RVE)
+ Calibre's hierarchical capability is very intuitive in pointing
out LVS and DRC errors.
+ RVE is also seamlessly integrated into both Mentor and Cadence
mask design tools. Full chip debug is amazingly fast.
- Integration between versions of Mentor's ICStudio and Calibre RVE
are not always 100% compatible. Users must beware of this prior
to updating to the latest versions. There does not seem to be
a problem with integration to Virtuoso.
I do not have enough experience to comment on their TVF (Tcl
Verification Format).
- Steven Chin of Stretch, Inc.
I'm a Calibre user for more then 10 years. Calibre RVE is one of the
best debug tools that I've used. It is easy to use, very fast and has
great violations debug capabilities. Very easy to track of shorts,
open or DRC - which lead to a very fast violation resolving. We also
found Mentor support very fast and efficient (when we need it).
- Chaim Hauzi of Metalink Broadband Ltd.
Calibre tool-suite and especially DRC/LVS are good.
- [ An Anon Engineer ]
We use Calibre DRC/LVS for all our physical verification. It has been
around so long so it has no real issues. However Magma LVS/DRC shows
some promising improvements in speed and size of rule decks (i.e. time
to create them).
- Michael White of Arrow Electronics
Calibre DRC/LVS are our physical verification tools. Their litho tools
are also used.
- [ An Anon Engineer ]
Calibre DRC/LVS is the best and easy to use. Others are not used.
- [ An Anon Engineer ]
Calibre DRC/LVS:
We use Calibre for DRC/LVS for 5 years. Do not think to replace it.
Very robust tool, user friendly and good support by Mentor.
Calibre xRC:
We use Calibre xRC for 2.5 years. We use it for parasitic extraction
from GDS, while for other types of extraction (DEF/LEF, Milkyway) we
use StarRC-XT. Calibre xRC was the 1st tool in the market to extract
in gate-level from GDS, in the quality requested by us. Currently
Calibre xRC has capacity limitation when extracting cross capacitance
of big P&R blocks. I was told that there is a beta version where
this issue was solved. Waiting to put my hands on it. We use xRC
also for transistor level extraction. The performance is pretty good.
The tool is not bug free, and sometimes there are connectivity issues
in the extracted netlist. Mentor is working to solve this issue.
- Eyal Landesberg of Zoran
We use Calibre DRC/LVS and are very pleased; xRC is under consideration
for our next generation products.
- [ An Anon Engineer ]
Calibre works well in 130 nm and 90 nm, but in 65nm it is unknown.
- [ An Anon Engineer ]
Calibre is the standard in physical verification.
- [ An Anon Engineer ]
We are starting to re-evaluate Calibre xRC. When we examined it several
years ago, Mentor claimed that they started including inductance, but
their calculations were way off. This extractor has shown enough
progress for us to formally evaluate it again.
- [ An Anon Engineer ]
Calibre DRC is still the standard, and it is counter-productive not to
have your design go through it before sending it off to UMC/TSMC.
- [ An Anon Engineer ]
Index
Next->Item
|
|
