( ELSE 06 Item 23 ) -------------------------------------------- [ 06/23/06 ]
Subject: Calibre DFM, Aprio, KLA-Tencor, Nannor, ChipMD, LogicVision
MIKE AND ATUL -- To get a first look at the exotic world of DFM, I asked the
CEOs of two DFM start-ups what they specifically thought about their niche
and their rivals. It resulted in ESNUG 453:
( ESNUG 453 Subjects ) ------------------------------- [03/01/06]
Item 1: Mike and Atul go to the DFM movies
Item 2: Mentor, Cadence, Synopsys, Magma, PDF Solutions
Item 3: Aprio, Clear Shape, KLA-Tencor, Brion, Invarium
Item 4: Luminescent, Takumi, Blaze DFM, Nannor, Sigma-C
Item 5: Ponte, Prediction, SDS, Pyxis, Pulsic
Item 6: Praesagus, Sagantec, TSMC, SoftJin
Item 7: ChipMD, Silicon Dimensions, LogicVision
Item 8: and if you're enraged
And, of course, there were the user comments I got from this survey, too.
Calibre DFM tools are used. Synopsys tools have been evaluated and
have some promise.
- [ An Anon Engineer ]
Calibre DFM works for us. Of all the rest, only Synopsys appears to
have a roadmap to get to a complete solution, but it's not there yet.
- [ An Anon Engineer ]
Design for Yield
The two big issues here are:
1. There is no standard for transmitting yield information from a
foundry for someone trying to improve their yield.
2. This is the most sensitive information that foundries possess
so they will demand some sort of encryption.
A number of tools would gladly accept foundry specific information and
change the layout in keeping with their utility. Currently there is no
way universal method to do that and I'm not aware of anyone working on a
standard. For example, Synopsys IC Compiler measures "critical area"
(the total area where a particle could cause a failure) and tries to
minimize it. They said they would gladly take more exact, foundry
specific information but can't get any. Mentor is also working on some
standard encrypted format but currently has to let the user make guesses.
Mentor's Calibre is a major player in the design for yield area and most
other vendors were comparing their tools to this. Their tool does full
analysis and limited modification to improve yield.
Aprio sells DFM software to do the OPC and RET, simulate it and fix
small areas. They claim it is similar speed-wise to Calibre.
Nannor sells a tool that does fixes based on recommended rules. It can
do things like redundant vias, line end spacing changes, avoidance of
stacked vias, and wire spreading. The user can also specify new rules
using the Tcl interface.
Ponte sells a tool that analyzes yield detractors. The input is GDSII
or LEF/DEF plus fab information, and the output is detailed yield
information. It gives yield by layer, highlights worst yielding nets,
etc. They can characterize libraries and IP.
CommandCAD sells fast pattern matching software that looks for yield
detractors that might still pass DRC checks. They say they can spot
areas where OPC will have problems. They emphasized that their approach
is 2D, unlike 1 dimensional DRC checks. They get yield information
from the fab (format??).
KLA has a tool called Design Scan that allows full chip process window
simulation. The input is the mask data after OPC. They claim that in
only 2-4 hours they can simulate an 8mm by 8mm die over 35 focusing
exposure conditions. They have an older tool called Prolith that is
aimed more at simulation of individual cells.
Sigma-C sells what they claim is the only tool to do 3D resist sim.
The depth of focus of modern equipment is extremely small, so 3D
simulation, which models how the resist is developed throughout its
height, can spot problems that normal 2D simulation can't. The problem
is that is it amazingly CPU intensive. Currently their tool can only
do a small portion of a cell. A new product due out later should be
able to do an entire standard cell.
ChipMD sells tools that do Design for Yield (at a circuit level, not a
mask level) for analog devices. One does circuit optimization for
yield using Monte Carlo simulation, and one does worst case analysis
without using Monte Carlo methods. Both create SPICE scripts for your
own simulator (they don't provide a simulator).
Clear Shape is a DFM company that had no products out yet as of DAC.
The Sagantec folks said they are getting lots of interest in their
Design for Manufacturability stuff. They say their customers have
working silicon at 65 nanometers and their tools are being used on
a 45 nanometer design. Their tool does things like doubling vias and
increasing overlap around vias as well as fixing DRC violations.
They also have a tool called Anaconda for analog checking. The user
can specify properties on a schematic (like symmetry) and the tool
checks for those properties.
Rubicad again did not attend DAC. I heard that at least last year they
just didn't think it was worth the money.
- John Weiland of Intrinsix Corp.
Sagantec are useful for process migration, but it starts choking on
advanced technologies. The ClearShape and Blaze DFM simulators look
interesting.
- [ An Anon Engineer ]
LogicVision adds value to some extent but it does require a lot of
understanding of new concepts and some changes to the flow. This is
OK for large companies, but for smaller companies, this may be quite
a deterrent.
- [ An Anon Engineer ]
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