( ELSE 06 Item 26 ) -------------------------------------------- [ 06/23/06 ]
Subject: Gradient FireBolt
THE WHOLE PACKAGE -- While ESNUG 454 #12 was the first hands-on user review
of the Gradient FireBolt thermal package EDA tool:
Our first question about Gradient was whether or not it predicted
real life thermal behavior of a chip, so we used a test chip used to
validate the tool for package temperature analysis.
actual Tj (C) FireBolt Tj (C)
Power JA measured average diode
Package (W) (K/W) using diode temperature
--------- ----- ----- ----------- -----------
Epad1 2.19 29.7 87 87.91
Epad2 2.18 29.4 86 86.97
Slug1 2.13 28.2 82 82.96
Slug2 2.12 27.8 81 81.88
Personally, I think this is a good indication of accuracy but a more
detailed investigation must be made.
It was interesting to get other people's take on the same tool; sort of like
that fable of 12 blind men describing an elephant -- they "saw" different
things even though it was the same animal.
Gradient: 16 people - startup
Tool: Firebolt, for dynamic simulation in RTL or transistor it ties
to Sequence PowerTheatre and Avanti HSIM.
Firebolt Description:
- tool to define temperature effects on chip in 3 dimensions
- temperature governs usual suspects - leakage and IR drop, and
timing, self heat, electro migration
- why timing - ids (saturation increases so does delay)
- why self heat - voids
- maybe good for automotive, wireless
- Firebolt uses Open Access (future enhancement is repair - that
will be tough!)
- inputs are LEF/DEF, GDS, technology (ASCII file which governs theta j)
Gradient Firebolt addresses a space we are interested in. There has
been precious little attention to temperature at the design phase.
- [ An Anon Engineer ]
I talked with the Gradient people at DAC but have no hands-on experience
with Firebolt. My view is that Gradient is the only vendor selling
temperature analysis tools. Other vendors such as Cadence and Apache
were saying that as far as temperature analysis goes, they will have
an interface with Gradient. This is certainly a strength of Gradient.
The temperature analysis market doesn't seem to be large enough to
attract competitors. In fact, we have fewer high-performance chip
designs for network applications in my company, but instead are looking
at more consumer-electronics type low-power designs. This will decrease
the temperature gradient in a chip and decrease the need for Gradient.
As a tool itself, Firebolt seemed to stand on sound basis of physics.
Its GUI looked nice.
- [ An Anon Engineer ]
Some of the examples that Gradient demoed of the difference between the
power map and the thermal map were surprisingly counter-intuitive. If
you only had the power map, you'd have made the wrong design choice;
which is why Gradient chose them for their demo.
I wasn't completely clear on how smoothly the FireBolt thermal analysis
fits into the place & route flow, and how tight the iteration loop was,
but in my view having it actually *in* the design flow instead of being
a post-implementation analysis is important. I was glad to see that
their analysis is a full system analysis, the die including the package
and the heat sink as well. Gradient says they're working with the fabs
to characterize their analytical engine to make sure FireBolt's numbers
are correlated to real lab-measured results.
The part that blew me away was the graphical display of the thermal
data. It can manipulate the physical dataset in 3 dimensions, such as
rotating the 3-dimensional surface of the temperature gradient, or
sifting through planes in the z-coordinate. It was actually fun to
view the data, and I can't say I've ever enjoyed that before!
While most designs at 130 nm probably won't have thermal gradients bad
enough to get much advantage from FireBolt, the higher-power designs
below 130 nm will need to perform this kind of analysis. It seems like
early days yet for this tool, but it aims to fill a need that becoming
critical, and it would be interesting to evaluate on a real project.
- [ An Anon Engineer ]
Gradient Design Automation is working on tools for temperature variation
across a chip. The input is LEF/DEF or GDSII, output from a power tool,
a description of the package (Gradient's own format) and technology
information (their format). The output is temperature by instance and
recommended changes to the placement. They are working closely with
Cadence. The analysis tool is shipping now and the repair tool is in
development but no release date is currently projected.
- John Weiland of Intrinsix Corp.
Gradient Firebolt was one of my top 3 products from DAC 05. From my
trip report slides:
Gradient FireBolt
1) Determines steady-state on-chip temperature variation (by layer)
2) Could be of some use now for package (and heat-sink) selection
3) Needs to partner with companies to model and/or process per-instance
temperature variation
I was so impressed by the tool and that I tried to organize a follow-up
evaluation. Unfortunately, that didn't work out because Gradient was
looking for a "big win" and my lab was looking to evaluate the tool as
a possible piece of our ASIC DA system in the next year or two.
I think the tool features and algorithm look strong. The graphics have
certainly gotten a lot of work. My greatest concern is that FireBolt is
looking at a third-priority form of variation (on chip process variation
and on-chip voltage variation are currently more critical).
For FireBolt to achieve broad use, library providers will have to model
for timing vs. temperature (when most aren't even ready to deliver
voltage variation models for signal integrity). Once the library models
are in place, then the tools (floorplan, physical synthesis & route)
will need to be updated (or at least verified) to work reliably with
the new data -- of which the Firebolt-calculated variability will be
one of many effects.
- Brett Johnson of Agilent
I saw a demo of Gradient's Firebolt thermal analysis product. The only
comment I can make is that it looks like a very comprehensive, well
engineered solution. Without further evaluation it's impossible to tell
whether it provides an accurate analysis. However, our initial reaction
is that Gradient has a solution looking for a problem. We have no
evidence that thermal intra-die variation is significant on our chips.
This would require further study.
- [ An Anon Engineer ]
I saw the FireBolt demo. It was interesting. Below 0.13 um process
the leakage current is very significant. Leakage is exponentially
dependent on temperature.
Using Firebolt we could loop between power and temperature until we
converge into a temperature value that is coherent to the power value
in different parts of the design. This could avoid over-design, and
improve leakage-temperature problems before tape-out. We are planning
to evaluate Firebolt, since it could be very useful for us.
- Evelyn Landman of Mellanox
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