( ELSE 06 Item 27 ) -------------------------------------------- [ 06/23/06 ]
Subject: Xpedion GoldenGate, AWR, Cadence Spectre RF, Ansoft
PEER PRESSURE -- In this survey I got beaten up by a user for not asking any
questions about RF tools. And after the thrashing, this person provided his
own detailed review of Xpedion GoldenGate. Fair enough. I found some more
analog/RF tool talk to keep this engineer happy.
I compared Xpedion GoldenGate side by side with Cadence Spectre RF,
Agilent RFDE, Mentor Eldo, etc. GoldenGate had won hands-down.
I initially compared an entire cellular downconverter chain, including
from RF to baseband filter, with about 5000 transistors, 30,000
parasitics, etc. For two closely spaced tones, using the same sun
sparc, Eldo took about 40 minutes, Spectre took hours, ADS would not
even converge, and GoldenGate solved this accurately in about
10 minutes. ADS has made improvements since then, but Agilent still
cannot get accurate or even realistic phase noise, and still have
issues handling large number of parasitics. For Eldo I could not get
the bug fixes to allow my other circuits to simulate, and ADS was not
willing to turn-around bug fixes fast enough to meet my stringent
tapeout deadlines. Spectre is an inherit time domain simulator,
therefore it will always have problems with parasitics and produces
gross approximations for S-parameter models in nonlinear simulations.
GoldenGate, time after time has implemented new features and bug fixes
within 2 to 3 weeks! Xpedion appears to be focusing its resources on
R&D for GoldenGate, while most big companies focus on their marketing
and sales force. GoldenGate had the best match to our measured phase
noise results. I think that R&D focus better meets my design needs.
- [ An Anon Engineer ]
Analog/RF Tools
Xpedion sells a frequency domain simulator tool called "GoldenGate"
(not to be confused with the IR drop analysis folks). They say is
better than the tools from Agilent or the recent competing tool from
Cadence. Interestingly, Cadence is an investor in this company. They
integrate into Cadence and take a Cadence design kit from the foundry,
and say most new customers are up in only one day. They are proud of
their support team, which they say is larger than those of the
competitors combined. They are also proud of the capacity of the tool,
which they say can do an entire radio chain at the transistor level
with parasitics. They have a new browser that allows users to preview
waveforms without tying up a simulator license. It allows the user to
copy the waveform to a clipboard, save the image for use in Microsoft
docs, or email the waveform in an ASCII format.
Agilent says their frequency domain simulator has better capacity and
performance than their competitors, and says they've done designs as
large at 17K transistors. They are now moving into simulation of PLLs
for jitter, etc. and are integrating their EM tools into the Cadence
environment.
Sagantec has a tool called Anaconda for analog checking. The user can
specify properties on a schematic (like symmetry) and the tool checks
for those properties.
Mentor sells a set of tools (schematic capture, simulation and layout)
for analog/RF design and says their edge is in mixing analog and RF in
simulation of a large system.
Applied Wave Research sells several tools for analog and RF design.
Most tools plug into a Cadence environment. They can do schematic
entry and simulation using both HSPICE and their own frequency domain
simulator. Their signal integrity design suite can simulate a PCB,
package, bonding wire and chip in a single simulation. They also have
a high-level system design tool for communications systems that can
simulate things like bit error rates.
Ansoft sells an environment for RF design, including a simulator that
operates in both time and frequency domains. They also have two tools
for EM/signal integrity analysis. One is a full 3D tool that has the
necessary accuracy for cables, wire bonds, connectors, etc. and the
other is a 2.5D tool that is faster and good for packages and PCBs.
Anasift Technology sells a tool for analog optimization. The input is
a netlist and the output is a sized netlist. They have their own
simulation engine, which they claim is within 0.1% of HSPICE. Their
tool can do symbolic analysis; extract a transfer function and does
unlimited corners and parameters. They claim that, unlike many competing
tools, their tool needs no good starting point to do an optimization.
They typically run optimization with a small number of corners, then
verify with all corners. If it fails, they optimize again using the
corners that failed. In one benchmark, they did 3 op amps. These had
taken 4 weeks to do prior. With their tool it took 1 day, saving a
total of 10 man-weeks.
Orora sells two analog/RF tools. The first takes a design, expressed
in a Cadence schematic or SPICE netlist, and then derives equations
for it, allowing analysis of poles and zeros, sensitivity, etc. The
second selects a topology from ones you provided, optimizes the design
and does a yield analysis ("analog synthesis" - netlist to sized
netlist). They use whatever simulator you have and can support
multiprocessing.
Berkeley Design sells a tool for analysis of Phase Locked Loops. It
analyzed phase noise and does jitter design. They say it has been used
on 35 designs in 12 different processes.
ChipMD sells tools that do Design for Yield (at a circuit level, not a
mask level) for analog devices. One does circuit optimization for
yield using Monte Carlo simulation, and one does worst case analysis
without using Monte Carlo methods. Both create SPICE scripts for your
own simulator (they don't provide a simulator).
OEA sells tools for RF component analysis, inductor design and 3D
inductor analysis.
Lorentz Solutions sells tools to create passive components. Their tools
support EM design and verification, and support EM coupling. They claim
their tools are faster than the competition, and say they can design an
inductor in 1-2 minutes.
Triad Semiconductor sells a mixed signal Structured ASIC that is
customized with only one mask layer. They feel their sweet spot is
from around 5K to 100K parts.
Accelicon Technologies sells an analog virtual prototyping tool. The
input is a Cadence Composer schematic. It writes constraints and created
a floorplan. The user can modify the constraints and do what-if analysis
to quickly examine alternative floorplans. The output is a Cadence
database. They say that for a 250 device design they can go from
schematic to layout in 8 minutes.
- John Weiland of Intrinsix Corp.
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