( ESNUG 148 Item 1 ) ---------------------------------------------- [9/9/93]
From: Synopsys Hotline
Subject: Using Extended Error Messages
Many error and warning messages that customers experience within the
Synopsys Toolset now have Extended Error Messages. These EEMs provide
a more detailed explanation of what could be causing an error message
as well as in-dept "NEXT STEP" sections.
In order to gain access to these messages while working within the
tool, simply enter "help" followed by the message. For example, to
read the EEM for the following message:
OPT-205 (error) Inconsistent references found for cell '%s'. (OPT-205)
simply type:
dc_shell> help OPT-205
This will return the following message:
Command Reference N. Messages messages
NAME
OPT-205 (error) Inconsistent references found for cell
'%s'.
DESCRIPTION
This is an internal Design Compiler error which
indicates that two references by the same name have
different port interfaces.
WHAT NEXT
Ensure that no library cells addresses conflict. An
example is a design named AND2 with ports I1, I2, 01
and a library cell of the same name with ports A, B,
and Z. In this case changing the name of the design
will solve the problem.
V3.0 Synopsys Inc. 1988,1989,1990,1991. All rights reserved. n-1
NOTE: The first set of extended error messages for Synopsys synthesis
tools appeared in v3.0a, and set was expanded in the v3.0b. Extended
error messages for Synopsys simulation tools will first appear in v3.1a.
- Synopsys Hotline
( ESNUG 148 Item 2 ) ---------------------------------------------- [9/9/93]
From: homberg@beorn.hw.stratus.com (Mike Homberg)
Subject: Mystery Memory Allocation Errors
John,
We have been getting an error message from synopsys3.0b:
"Error: internal memory allocation error."
This is from dc_shell_exec running on an hp755. The error message comes out
on standard error not standard output. The job keeps running but we
suspect that it's giving up at certain points judgeing by our timing results.
Synopsys claims that it's not them but I found the strings in the
dc_shell_exec binary file so it is coming from Synopsys.
It happens quite often but is not easily repeatable. Perhaps due to other
jobs using memory on the server. We have to go back to synopsys3.0a for now!
We have also seen it on a sparc10 with is slightly different error message.
Anyone else seen this?
- Mike Homberg
Stratus Computer
( ESNUG 148 Item 3 ) ---------------------------------------------- [9/9/93]
From: Alan Bair <abair@amcu-tx.sps.mot.com>
Subject: What Can I Safely Delete After A Synopsys Install
Hi John,
I'm working on installing Synopsys 3.0b to test it out. We also use Synopsys
2.2 and 3.0a-10063, so the disk space usage is getting rather high. We only
use the synthesis and SIFF part of the Synopsys tool set, but everything
gets loaded. So I was looking into trying to delete some of the unused stuff,
primarly the VHDL simulator files.
It looks like I could safely delete the directories:
packages
<arch>/packages
xilinx
doc (if desparate for space, user's don't RTFM anyway :)
Has anyone else done this and not managled things? Are these OK or are there
any other easily deletable parts? Sure would be nice if Synopsys would load
stuff selectively, espcially now that it is on CD-ROM.
- Alan Bair
Motorola, Inc.
( ESNUG 148 Item 4 ) ---------------------------------------------- [9/9/93]
From: uunet!uranus!joker!martin (Martin Gravenstein)
Subject: Clock Tree Insertion
Let's say a systems type writes and HDL for a circuit he would like VLSI
integrated into an ASIC. The HDL becomes functionally perfect and provides
satisfactory optimization and performance based on sepcified timing
constraints and an area target for a particular vendor's CMOS library. Now
this guy has been synthesizing his single phase, flip-flop based, synchronous
design with the default ideal Synopsys clock. He of course now has several
hundred flops connected to a single clock signal. He recognizes that a
balanced clock tree must be created and inserted. He would then be
interested in hearing suggestions from other designers on how they
accomplished this task. He would be concerned on how these designers:
1) determined the necessary size of the tree
2) chose the flops to be connected per branch to assure least
susceptability to clock skew
3) where & how the netlist was modified to reflect these new connections
What do you think those designers would tell him?
- Martin Gravenstein
Ford Microelectronics
( ESNUG 148 Item 5 ) ---------------------------------------------- [9/9/93]
From: jcooley@world.std.com
Subject: report_timing Doesn't Like Busses But Individual Bits
Inside a simple FIFO design I ran into some post synthesis hold violations
in simulation. (This kind of surprized me because all the Synopsys reports
seemed happy concerning all the timing constraints.) Anyway, the simulation
said that the address pins on the dual port memory instantiated in
the FIFO had the hold problems. I went back into Synopsys to double check
things. (BTW the memory instance name is "mammy" and the address pins are
a multi-bit vector called "A".)
Here's what I found:
dc_shell> report_timing -to mammy/A
Warning: Can't find object 'mammy/A' in design 'fifo'. (UID-95)
Error: Design object list required for the '-to' argument. (EQN-19)
.
.
.
But when I did asked Synopsys about a specific bit in "A", I got:
dc_shell> report_timing -to mammy/A[0]
Performing report_timing on pin 'mammy/A[0]'.
Startpoint: pointer_reg[5]
(rising edge-triggered flip-flop)
Endpoint: mammy (rising edge-triggered flip-flop)
Constraint Group: (none)
Path Type: max
Point Incr Path
-----------------------------------------------------------
pointer_reg[5]/CLK (DFF) 0.00 0.00 r
pointer_reg[5]/Q (DFF) 1.74 1.74 f
mammy/A[0] (mem_512x16) 0.00 1.74 f
data arrival time 1.74
-----------------------------------------------------------
(Path is unconstrained)
What this means is that Synopsys doesn't like vectors, but single
bits as far as "report_timing" is concerned in rev. 3.0b. My gut hunch
is that there is probably a whole set of Synopsys commands that dislike
vectors but I don't have the time to search them out.
- John Cooley
EDA & ASIC Design Consultant
(and the ESNUG guy, too!)
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