( ESNUG 161 Item 1 ) ---------------------------------------------- [11/5/93]
Subject: ( ESNUG 160 #1) "Verification Error Problem & Solution"
> We had a verification error with one of our VHDL synthesis runs.
>
> Basically, the synthesis did not handle sign extending the operands by
> assigning the upper bits from the lower bits. Instead, the upper bits had
> to be assigned a constant based on the lower bits.
>
> Example VHDL that would work:
>
> sum_A <= '1'&'1'&'1'&u_1d when u_1d(8) = '1' else '0'&'0'&'0'&u_1d;
>
> Example VHDL that wouldn't work:
>
> sum_A <= u_1d(8)&u_1d(8)&u_1d(8)&u_1d;
From: [ Anonymous ]
John, for company B.S. reasons, please keep me anonymous.
In this post, the user had a problem with sign extending using concatenation
when trying to verify his design. While I haven't had the same problem with
verification, I have had problems with concatenation. I wonder if he knows
about the functions SXT and EXT that are in the Synopsys Arith package. This
is what I would use. (Where SXT is sign extend, and EXT is zero extend.)
At our site we don't use VSS either but rather we set up our Mentor system
so that when we call out library IEEE, the Synopsys packages that we normally
use for synthesis, are automatically used during compiling and simulation.
Perhaps this could be done somehow on the Viewlogic simulator that this person
is using to aid in ease of portability??
Anyway, hope this helps in some way.
- Blackmailed into Anonimity.
( ESNUG 161 Item 2 ) ---------------------------------------------- [11/5/93]
Subject: (ESNUG 160 #4) "VSS VHDL SDF Timing File Bug"
> I have run into a bug in Design Compiler that can produce a misleading VSS
> simulation. The problem is when writing out an SDF timing file, Design
> Compiler will only write one triplet for both the rise and fall delays.
>
> Equal rise / fall delays can occur in the interconnect delay and some
> special cells. The SDF file from design compiler will look like:
>
> (INTERCONNECT U4/X RAM1/RWB (1.001:1.001:1.001))
>
> when U4 is back annotated in VSS only the rise delay is set to 1.001 ns !
>
> What I need is :
>
> (INTERCONNECT U4/X RAM1/RWB (1.001:1.001:1.001)(1.001:1.001:1.001))
From: dan@qlc.com (Dan Pinvidic)
John, here is a simple sed command which will modify a sdf file generated
by Design Compiler by adding the second triplet for fall time.
- Dan Pinvidic
QLogic Corp.
NOTE: the first line of the script must be a blank comment line!
#
# This C shell script will duplicate the rise triplet set in each line
# which has in interconnect command. Calling this script and supplying one
# argument (sdf_file_name) will send the results to standard output. If the
# results look correct, redirect the output to a new file name.
#
# Usage: modify_sdf sdf_file_name >redirect_file_name
#
# Remember - The "Regular Expression" is you friend!!!!!!
sed -e '/INTERCONNECT/s/\(([0-9:\.]*)\)/\1\1/' $1
( ESNUG 161 Item 3 ) ---------------------------------------------- [11/5/93]
From: [ Synopsys Product Marketing ]
Subject: Synopsys Support for Mentor Falcon 8.2_5
Mentor Graphics recently released the 8.2_5 version of the Falcon framework
(an upgrade from 8.2_3). To support this release, the Synopsys is releasing
a patch for the current SIFF (Synopsys Integrator to the Falcon Framework)
product. Synopsys has been working with Mentor to quickly support new Falcon
releases, and will make the patch available through our sales and field
support offices by December 3. This patch is fully tested for production
release and is keyed on existing SIFF licenses.
The SIFF patch supports the current v3.0b releases on both SPARC and HP700
platforms. This patch should be installed only at sites upgrading to the
most recent Falcon v.8.2_5 release. For all new SIFF orders shipping after
December 3, the SIFF patch and documentation will be automatically included
in the product package. For the Synopsys v3.1 release, the Falcon 8.2_5
interface will be built into the SIFF product, and the patch will not be
required.
- Synopsys Product Marketing
( ESNUG 161 Item 4 ) ---------------------------------------------- [11/5/93]
From: monks@azmda.sps.mot.com (Morgan Monks)
Subject: SDF Bus Notation Problem - Works When Broken, Won't When Fixed!
John:
I can't get design compiler to write an SDF timing file out using bus
notation which will agree with the VHDL file written at the same time.
What I get is:
(INTERCONNECT A\(7\) RAM1/Ax7x (0.000:0.000:0.000))
What I need in Vss for back annotation is:
(INTERCONNECT A\(7\) RAM1/A[7] (0.000:0.000:0.000))
Synopsys keeps insisting to set the variable:
read_array_naming_style = %s[%d]
An important detail to this problem SFD file bus notation is my example
contains a RAM cell which is a behavioral model only. If you _FAIL_ to
properly link to the library model for the RAM, the SDF file has buses of
the correct format of A[0]... !
BUT -- when the RAM is correctly linked into the design in DC you get (you
guessed it) the wrong bus format of Ax0x !
That is: when it's broken it works, when it's fixed, it won't work! :)
We do a lot of special cells for memories. I don't want to do "flat" models
for memories but I may have to do that. My only real work-around is to write
a script to modify the SDF file but I don't like the idea of having to
post-process SDF files. (I think it's dangerous to get in a habit of editing
these files.)
Any ideas ?
- Morgan Monks
Motorola HPMG Semi-Custom Division
P.S. Synopsys keeps telling me that I don't have a problem. They can't get
the RAM linked in so to them everything appears fine and dandy.
( ESNUG 161 Item 5 ) ---------------------------------------------- [11/5/93]
From: Marc Clarke <mic@hpfimic.fc.hp.com>
Subject: Synopsys Wire Model Area Not Used
John,
I just read ESNUG 157 and the discussion about the wire model's "area"
parameter. In the past I have asked the Denver Synopsys AE directly about
the use of the "area" factor in the wire model. He assures me Synopsys
does not use the "area" parameter at all during any phase of synthesis.
- Marc Illsley Clarke
Hewlett-Packard
( ESNUG 161 Item 6 ) ---------------------------------------------- [11/5/93]
From: mcdonold@e5sf.hweng.syr.ge.com (Michael S. McDonold)
Subject: Test Compiler Hates Same Names Throughout Hierarchy
John,
I have been getting some ESNUG postings forwarded to me on specific topics
that friends knew I'd be interested in seeing. I was recently sent both
Post #154, and #155, and the information and its application to what I'm
currently working on (Test Architecture & Test Insertion Process for a series
of ASICs) has been incredibly helpful. Rather than run the risk of possibly
missing a good post, I'd like to join ESNUG.
Keep up the excellent work!
And now I'd like to ask for some help. We are using Test Compiler to insert
the scan chains for a multiplexed flip-flop design, and using a special
soft-macro that the vendor created for us. Test Compiler handles the basic
task with flying colors, but before we write out the designs in structrual
VHDL to go to the simulator, or in EDIF to go to fault-grading, we need to
convert it into our vendors library primitives.
We have been unable to fool the tool into replacing the part with an
hierarchical part of the same name by any means but using an external link
for the files, and then changing to object that is linked. Has anyone run
into this problem before? When we make the macro library invisible to Test
Compiler, it uses the vendors normal scan parts even though they have the
dont_use attribute attached. There are several workarounds that we have
come up with, but they all require editing structural VHDL outside of
Synopsys.
- Michael McDonold
Martin Marietta Corporation
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