Looks like the hardware business is a little more risky than our college
professors let on. If you read this week's EE Times, Oki Semiconductor
was held up at gunpoint on Halloween for $2 million worth of DRAMs. The
article goes on to say there have been a string of such robberies recently
in Silcon Valley. (And my high school guidance counselor assured me that
electrical engineering wasn't a hazardous profession!) - John
( ESNUG 162 Item 1 ) ---------------------------------------------- [11/9/93]
Subject: (ESNUG 158 #4 159 #2 160 #2) 'Licensing Wars'
> What is the resolution? Synopsys wants me to buy enough HDL Compiler
> licenses to match 1-to-1 with Design Compilers. There has not been much
> give on their part in pricing or terms. They claim we are one of only a
> few companies which do not have parity in licenses (is this true? anyone
> else out there have the same problem?). We have suggested to Synopsys
> technical solutions such as "wait" for a license, turn off DesignWare,
> etc., but have been rebuffed so far.
--- --- --- ---
From: [ Anon ]
John, Please keep me anonymous for this one.
These are the licenses's we currently have. Since day one the Synopsys
Salesman said we only needed a few HDL-Compiler licenses.
FEATURE DC-Expert 4
FEATURE DC-SDF-Interface 4
FEATURE Design-Analyzer 5
FEATURE Design-Compiler 4
FEATURE HDL-Compiler 2
^
|
Number of licenses
- Anon
--- --- --- ---
From: hill@pau.synnet.COM (Shannon Hill)
John:
We, too, ran into this problem with the 3.0x-Design_Compiler-Needing-Its
-Own-VHDL-compiler license. Since we had only two Design_Compilers, and one
VHDL-compiler license, the transition from 2.2x to 3.0x cut our bandwidth
significantly.
We complained, and received an additional VHDL-compiler license, with the
assurance that the problem would be resolved in a future release.
I'm surprised that Synopsys didn't understand that changing the license
consumption model (even at a major release) is unacceptable corporate behavior.
- Shannon Hill
Synernetics
( ESNUG 162 Item 2 ) ---------------------------------------------- [11/9/93]
From: [ Synopsys Quality Engineering Department ]
Subject: 3.0a & b FPGA Compiler May Produce Incorect Logic - STAR 13749
The problems and workarounds listed below are of interest to FPGA Compiler
customers who use the Xilinx 4000 technology and v3.0.
FPGA Compiler has a problem with CLB optimization in the compile command for
the Xilinx 4000 technology. If a table-lookup output feeds to its own input
directly, then incorrect logic can result.
Suppose you had the following code:
module s13749 ( a, b, c, f0 );
input a, b, c;
output f0;
assign f0 = (a ^ b ^ c ^ f0);
endmodule
The block diagram would look like:
-----------------
a ------|F1 |
b ------|F2 X |------< f0
c ------|F3 cell 'a' | |
---|F4 | |
| | | |
| ----------------- |
| |
-----------------------
net 'f0'
Fig. 1: FPGA Design With Feedback Loop before compile
Then suppose you executed the following commands:
dc_shell> read -f verilog s13749.v
{"s13749"}
dc_shell> compile
For the Xilinx 4000 technology, the optimizer in the FPGA Compiler
has trouble with a feedback loop that is directly on the single lookup
table A. The optimizer might disconnect pin F4 in the resulting CLB,
resulting in the design:
-----------------
a ------|F1 |
b ------|F2 X |------< f0
c ------|F3 cell 'a' |
---|F4 |
| | |
| -----------------
___
_
.
Fig. 2: FPGA Design With Feedback Loop after compile
WORKAROUND
To work around this problem in v3.0a and v3.0b, create a level of hierarchy
for the logic that is contained in the feedback loop. It is important that
this level of hierarchy isolate the component(s) from the feedback loop; the
feedback connection should occur outside the new hierarchical block. The
example below illustrates this concept.
module s13749 ( a, b, c, f0 );
input a, b, c;
output f0;
floop f ( .a_in(a), .b_in(b), .c_in(c), .d_in(f0), .f_out(f0) );
endmodule
module floop ( a_in, b_in, c_in, d_in, f_out);
input a_in, b_in, c_in, d_in;
output f_out;
assign f_out = (a_in ^ b_in ^ c_in ^ d_in);
endmodule
Or graphically, this would be:
instance 'f' of design 'floop'
---------------------------------
| |
| ----------------- |
a ------|------|a_in | |
b ------|------|b_in f_out|--------|------< f0
c ------|------|c_in | | |
---|------|d_in | | |
| | ----------------- | |
| | | |
| | | |
| --------------------------------- |
| |
| |
| |
---------------------------------------
net 'f0'
Fig. 3: Workaround Illustrating Isolation of Feedback Loop
Note that the feedback net f0 is isolated from cell A by the instance f
of the new hierarchical design floop.
Note: The "group" command in dc_shell does not work in this situation,
because the command includes the feedback net in the new level of
hierarchy. You want the feedback net external to the new hierarchical
sub-design, so the new level of hierarchy must be introduced in the HDL.
PLANNING YOUR DESIGN
In your design process, you will often identify places where you intend to
use combinational feedback loops before you write design code. Building an
SR latch from individual logic gates is one example. However, if you do not
know the names of feedback loops, in an existing design, you can detect them
with the report_net command. The example below identifies net f0 as having
a combinational feedback loop in the design s13749.
dc_shell> read -f verilog s13749.v
{"s13749"}
dc_shell> report_net
Information: Updating design information... (UID-85)
Information: Timing loop detected. (OPT-150)
U1/h U1/z4
Warning: Disabling timing arc between pins `h' and `z4'
on cell `U1' to break a timing loop (OPT-314)
... net report ...
1
dc_shell> all_connected U1/h
{"f0"}
CAUTIONS
Feedback going through more than one component, such as feedback from net
f0 to cell B, which, in turn, drives cell A is acceptable and will not cause
the bad logic to occur (see Figure 4).
----------------- -----------------
| | a ------|F1 |
| | b ------|F2 X |------< f0
| cell 'B' | c ------|F3 cell 'A' | |
---| X |----------------|F4 | |
| | | | | |
| ----------------- ----------------- |
| |
-------------------------------------------------------
net 'f0'
Fig. 4: Feedback Loop Going Through Multiple Components
However, the logic in the feedback loop may be optimized down into a single
tlu (table look-up), so be careful.
- Synopsys Quality Engineering
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