> ANIMAL KILLER !!!! YOU SHOULD BE ASHAMED OF YOURSELF, BOASTING ABOUT
> SOMETHING LIKE THAT OVER A PUBLIC MEDIUM. HOW WOULD YOU LIKE IT IF THEY
> DID THE SAME THING TO YOU OR SOMEONE CLOSE TO YOU ???!
>
> - Member of 'People for the Ethical Treatment of Animals' (PETA)
Editor's Note: There were 17 responses (!) to "ANIMAL KILLER" and it seemed
that not one took the PETA side. Lots of people requested anonimity and wrote
some lightly humorous stuff. Here's a sample. - John "A.K." Cooley :^)
--- --- --- ---
I'm sure this guy doesn't wear leather belts and shoes or own a leather
wallet. I'm sure he doesn't eat any meat and it's obvious he doesn't have
anything fur in his house, including fur lined items such as gloves. This
is the type of guy who would have us living like the American Indians
centuries ago....Oh! But wait... there's that hunting deer and buffalo
thing that would get in the way! Well, there's always nuts and berries.
--- --- --- ---
I've enjoyed your occasional anecdotes from the farm and the technical
banter that follows. ESNUG is part of our success. Oh and - pass the
lamb chops and gravy please...
--- --- --- ---
I once got into an argument (sound like a Monty Python skit?) with a vegan.
Accused her of the heartless and thoughtless massacre of millions of
innocent celery stalks. She went ballistic! 8-)
--- --- --- ---
[ long personal attack on PETA member deleted ]
... And besides, I love rack-of-lamb!
- [Name Deleted], Member of META (Meat Every Time Available)
( ESNUG 168 Item 1 ) ---------------------------------------------- [12/93]
Subject: (ESNUG 167 #5) Synopsys "Ghosts" Haunting Our CPU AFTER Quiting
> We are struggling with a quite serious "ghost" problem on our SPARC2. They
> are equipped with 128 MB and 500 MB Swap as a local swap_file. When leaving
> Synopsys (by either quit or kill), the CPU gets heavily loaded for a few
> minutes (up to 10 minutes). During this time nothing else is running, no
> cursor, no clock, no nfs-daemon, no license-server etc. This means, other
> Synopsys-jobs that are going to read or write files on any disk connected to
> this system are crashing. Even jobs, not working on these disks get in
> trouble, as one of these SPARCs is our license_server.
--- --- --- ---
From: mark@e5sf.hweng.syr.ge.com (Mark Warren)
We saw a similiar problem which consisted of either the machine getting
'hosed' while Synopsys was letting go of its swap or having large Synopsys
processes going into "Disk Wait" forever.
The fix was to upgrade our operating system from SunOS4.1.1 to 4.1.3. I
believe 4.1.3 has better memory management.
Now if we could take advantage of multi threaded applications in Solaris 2...
- Mark Warren
Martin Marietta
--- --- --- ---
From: jaime@brahms.amd.com (Jaime Tolentino)
John:
This problem seems similar to ours but it may not be the same: We experienced
it whenever big Verilog jobs (lots of memory being used) finished.
It does seem to have been solved by SUN, though. (I suggest talking with SUN
about it and asking for a solution.) However, it may take time to solve.
When we had the problem, SUN did not recognize it right away. They started
putting in patch after patch. Finally, I believe the OS we have is 4.1.2
with several special patches thrown in. It may just be solved by going to
the latest OS version, but it is frustrating.
- Jaime Tolentino
AMD
--- --- --- ---
From: jericho!gord (Gord Wait S-MOS Systems Vancouver Design Center)
I too have noticed my Sparc2 get tied up for long periods of time during the
exit from Synopsys. I also get the same results from a large Verilog
simulation. The machine is so busy that it times out network accesses and
holds things up on our net. (My theory is that the OS is clearing out virtual
memory.) The bigger the job, the longer it takes. (i.e. if your process
grabbed 400 meg of ram, it probably takes a while to give it back, and clean
it up for other processes.
Its only my theory, and I too would like a reasonable fix. Perhaps nice'ing
the job would help? (I sort of doubt it..)
- Gord Wait
S-MOS Systems Vancouver Design Center
P.S. the one good thing is it discourages others from signing on and stealing
cycles from your Synopsys runs! :)
( ESNUG 168 Item 2 ) ---------------------------------------------- [12/93]
>John, using Synopsys (and VHDL), presently I'm attempting scan insertion of
>a multi clock device. Know what? Test Compiler isn't set up for multi
>clocked devices! It happily routs scan chains from one clock domain to
>another and back. No worry about setup and hold -- doesn't even recognize
>there is a problem!
--- --- --- ---
From: RYGK80@WACCVM.corp.mot.com (John Vogel)
John, try using:
insert_test_scan_chain_only_one_clock = true
(Do a "man" on this variable to see what it does.) The default value is set
to false and as such allows scan chains to be built with more than one clock
per chain. Note: v3.1a will default to single clocks per chain and a command
line argument to insert_scan will be introduced to provide control.
- John Vogel
Motorola ASIC
[Editor's Note: Two others also independently wrote similar replies. -John]
--- --- --- ---
From: victor@truevision.com (Victor J. Duvanenko)
A year ago I finished a chip that had two asynchronous clocks with four
scan chains, and Synopsys Test Compiler worked great. I was very careful
about spliting the chip into two parts - each part running on a single clock.
Then each clock portion was split into two halves to make the scan chain a
bit shorter. I also remember looking at the test vectors and timing
definitions that Synopsys generated. Synopsys clocks scan chains very
carefully, especially when there are two clocks. The two clocks would
transition with hundreds of nanoseconds between any edges, so there was
plenty of time for output of one scan-chain that runs on one clock to
propagate to a chain that ran on another clock. So I recommend looking at
the vector file that Synopsys generates and convincing yourself that it will
work, or running the vectors through a gate-level simulator where you'll
actually see what Synopsys is doing.
What we found, however, is that Synopsys was not very good at clock and
'not clock' scan-chains. They may have fixed it by now, but when I did it
I had to tell the Test Compiler not to scan those FF's that ran on 'not
clock'. This is less than optimal, of course, especially when there is no
potential problems that exist feeding logic that runs on clock to 'not clock'
logic (or vice versa), in fact the hold times are better in those cases that
are in a scan-chain that runs on the same clock.
- Victor J. Duvanenko
Truevision
( ESNUG 168 Item 3 ) ---------------------------------------------- [12/93]
Subject: (ESNUG 166 #2 ESNUG 167 #1) "DC Expert & DC Professional"
>> john, what are multiple clocks of the same frequency? do you mean multiple
>> clocks of exactly the same waveform? or do you mean multiple clocks of the
>> same frequency but with rise times shifted? or do you mean multiple clocks
>> of the same frequency with edges matched, one positive, one negative?
>
>From: [ Synopsys R & D ]
>
>The answer is simple: DC Professional handles an arbitrary combination
>of clocks as long as they have the same period. Each clock may have
>just two edges, but there is no restriction on where the edges must be.
From: [ NoName ]
Please withhold name...etc....
The user should watch out with this advice from R & D! Treating two clocks
with separate routing as the same just because they have the same frequency
is VERY DANGEROUS.
Such a design may be very prone to failure due to clock skew between the two
clock zones. (The same as in using ATPG with multiple scan chains.)
- [ NoName ]
( ESNUG 168 Item 4 ) ---------------------------------------------- [12/93]
From: jv@brooktree.com (jv eberst)
Subject: Design vs Reference ?
what is the difference between a design and a reference?
i had a hierarchical instance that was "dont_touch-ed"
> get_attribute find(cell,mycell) dont_touch
Performing get_attribute on cell 'mycell'.
{"true"}
but then i couldnt remove dont_touch with
> remove_attribute find(cell, mycell) dont_touch
Performing remove_attribute on cell 'mycell'.
Warning: Can't remove attribute 'dont_touch' from object 'mycell'. (UID-339)
{}
and
> remove_attribute find(design,mydesign) dont_touch
Performing remove_attribute on design 'mydesign'.
Warning: Attribute 'dont_touch' does not exist on design 'mydesign'. (UID-101)
{}
but i could successfully
> remove_attribute find(reference,mydesign) dont_touch
Performing remove_attribute on reference 'mydesign'.
{"mydesign"}
huh?
- JV Eberst
Brooktree
( ESNUG 168 Item 5 ) ---------------------------------------------- [12/93]
From: umj@ki.ericsson.se (Magnus Jacobsson)
Subject: dc_que - Script Waits for Design Compiler & VHDL Compiler Licenses
Hi John,
We're using this script to get around the fact that we don't have an unlimited
number of Design Compiler licenses and even fewer VHDL Compiler licenses.
It tries to start Design Compiler and, if no license is available, retries
every ten seconds until it gets one. Once started, it does the same thing for
a VHDL Compiler license.
The name of the script is dc_que and it is used instead of dc_shell, i.e.:
> dc_que -f my_script.dc
[ NOTE: The "\" is interpreted as continuing the same line. If this doesn't
work on your system, edit the two lines between "\" to be one long line.]
dc_shell -x "get_license VHDL-Compiler; while ( dc_shell_status == 0 ) \
{ sh sleep 10; get_license VHDL-Compiler;}" "$@"
while test $? -ne 0
do
sleep 10
dc_shell -x "get_license VHDL-Compiler; while ( dc_shell_status == 0 ) \
{ sh sleep 10; get_license VHDL-Compiler;}" "$@"
done
I hope this can be of use to someone and maybe even bring a truce into the
Synopsys License War.
- Magnus Jacobsson
Ericsson Radio Systems
( ESNUG 168 Item 6 ) ---------------------------------------------- [12/93]
From: Micheal O' Regan <micheal@s3dub.ie>
Subject: Seeking A Run Duration Rule-of-Thumb
Hello J. Cooley,
Can anybody out there give me some 'rule-of-thumb' information for the
improvements in synthesis run-durations you could expect if you upgraded a
Sun Sparc10 from 64MBs internal memory to 128MB, 256MB?
I imagine that this is going to be design-dependent but for a given design,
did anybody notice the improvement to be linear?, exponential?, bizzare?
- Micheal O'Regan
Silicon & Software Systems, Dublin, Ireland
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