[ And I thought I was having a bad day! - John ]
From: john_d@s3dub.ie (John Dillon)
Hello John. Some people here in S3 are already in your E-mail Synopsys
Users Group, but they're too mean to share your messages with me. I'd
appreciate it if you'd put me on your list. Thanks in advance.
- John Dillon
S3, Ireland
( ESNUG 178 Item 1 ) ---------------------------------------------- [2/93]
Subject: (ESNUG 175 #5) "How About Infering M/S FF's With Test Compiler?"
> I have a design in which I want to infer a Master/Slave flip flop that has
> two clock input pins "clk" and "clkn." Is this possible using Verilog and
> Synopsys? In addition will Synopsys Test Compiler support such an inference?
--- --- --- ---
From: kamphuis@troja.hl.siemens.de (Peter_Kamphuis)
Several years already we were using our library which contains Master-Slave-
Latches. (According to Synopsys a Master-Slave-flip-flop consists of two
flip-flops, a Master-Slave-Latch is one device with two internal latches.)
We are currently using VHDL, but there should be no problem to convert the
following example into Verilog.
We are also interested in other peoples experiences with Master-Slave-
Latches. Has anyone found a convenient way to use the sequential DesignWare
modules together with Master-Slave-Latches?
Since V2.2 it is possible to infer them automatically using the
"clocked_on_also" attribute. In V3.0 you can also use multiple clock pairs
and V3.1 will not bring anything new. The library you use should describe
the Master-Slave-Latches with the "ff" statement and define the Master-
Clocks (clk) as "clocked_on" and the Slave-Clocks (clkn) as
"clocked_on_also". Setup/Hold timing is bound to the Master-Clock, output
timing is bound to the Slave-Clock.
Now all you have to do is add an additional clock port to your HDL description
and set its signal type to "clocked_on_also". Synopsys will do the rest!
entity MY_MS is | architecture A of MY_MS is
port( D,MC,SC : in Std_Logic; | begin
Q : out Std_Logic ); | process
-- pragma dc_script_begin | begin
-- set_signal_type clocked_on_also SC | wait until MC = '1';
-- pragma dc_script_end | Q <= D;
end MY_MS; | end process;
| end A;
Unfortunately the additional Slave-Clock (SC) gets connected very late during
compile so timing optimizations may not be correct and another compile may be
necessary. Note that it gets more complicated if you want to keep pre- and
post-synthesis simulations compatible. (SC as clock in (V)HDL.)
With Test Compiler we use the LSSD method. The replacement Master-Slave-
Latches have an additional Scan-Master-Clock and Scan-In. In the test_cell
description the Scan-Master-Clock is defined as "test_scan_clock_a" and
Slave-Clock as "test_scan_clock_b". Normally no problems occur with
Test Compiler and our Master-Slave-Latches.
- Peter Kamphuis
Siemens Semiconductor Group, Munich
( ESNUG 178 Item 2 ) ---------------------------------------------- [2/93]
Subject: (ESNUG 175 #6 176 #2 177 #2) "Rev 3.0c Hates Making Clocking Networks"
>Hello, John. I am having problems with the balance_buffer command. I have
>a design in which different clock nets have to be buffered. The Design
>Compiler processes the circuit for a very short while... But when I
>inspect the design, I notice that nothing has changed! - massive fanout
>violations everywhere and no buffers at all were inserted!
--- --- ---
From: [Synopsys Corporate Applications Engineering]
In (ESNUG 175 #6), Maurizio Paolini said that he is having problems with the
'balance_buffer' command. A reminder to those who are using balance_buffer:
Synopsys does not recommend using balance_buffer for clock tree synthesis,
because the balance_buffer command does not calculate clock skew!
Unfortunately, there is a new bug in the v3.0c release that prevents the
balance_buffer command from working properly. The current implementation
does not recognize the max_fanout, max_capacitance, and max_transition
values, and does not use these values in its calculations. This bug has been
fixed in the upcoming v3.1a release.
A workaround for this problem is to use the set_max_fanout command on the
already mapped design, then 'compile' with the -only_design_rule option.
That will buffer your design in accordance with the max_fanout you set.
Alternately, you may also use set_max_capacitance or set_max_transition
with 'compile -only_design_rule'. Remember to compile the design first with
the necessary constraints before using the workaround.
Note: This workaround will constrain all paths in the design.
- [Synopsys Corporate Applications Engineering]
( ESNUG 178 Item 3 ) ---------------------------------------------- [2/93]
Subject: (ESNUG 173 #2 174 #1 177 #3) 3.0c DC + High Map = Crashing SPARC 10's"
>>If I compile Verilog source with the design_compiler using '-map_effort
>>high', after about 15 minutes the work station will trap to the boot prompt
>>with the message "watchdog timeout"! ... Any setting other than
>>'-map_effort high' appears to work OK.
>I'm sorry to report that we can't seem to reproduce Mark's problem either
>at Synopsys or at his local FAE field office. ... I'm lead to believe the
>problem to be due to Mark's c-shell scripts... - [Synopsys Support Center]
--- --- ---
From: mark@hweng.syr.ge.com (Mark Warren)
This seems to be a h/w problem with Sun. We have seen this happen to only 1
of the 7 Sparc 10's that we purchased recently. It seems to be fairly random,
and can happen while in Synopsys or a different vendor's simulator. The
people at Sun seem to be baffled. Have the faulty workstations replaced.
- Mark Warren
Martin Marietta
( ESNUG 178 Item 4 ) ---------------------------------------------- [2/93]
[ Editor's Note: What follows is an invited review of NeoCad's commercially
available FPGA place & route tools. Because engineers can't get realistic
reviews of new & current EDA tools from our industry's trade rags, I've
purposely instructed Bob to "Write about what the tools do functionally
first. Then describe your experiences with them. Please not all sunshine
& hapiness; but a critical analysis of these new products." As always,
this is one user's opinion -- Bob's not speaking for anyone but himself and
he's sharing his own first hand experiences. Enjoy. - John Cooley ]
From: bobh@oakhill-csic.sps.mot.com (Robert Hoffman)
Subject: One User's Review of NeoCad's FPGA Release Tools
John, the NeoCad software is a third party solution for the place and route of
FPGA's. It supports a number of FPGA types, including Xilinx and Actel. The
tool set is a complete substitution of the software normally supplied by the
FPGA vendor, and offers a migration path between FPGA types. This means that
a design initially targeted for Xilinx can be easily retargetted for Actel
and visa versa.
The first step to using this, or any, FPGA place and route software is to
generate an EDIF 2 0 0 netlist of your design. This netlist should be built
from appropriate FPGA primitives; these may be Xilinx symbols or Actel
symbols. NeoCad immediately converts this EDIF output into a NeoCad's own
primitives based netlist. It then maps the logic into the Combinatorial
Logic Blocks (CLB's) of the targetted architecture. Next step is the routing
of the interconnect, during which it moves assigned CLB's as necessary.
This is the most time consuming part of the effort, and takes even longer if
your using the Timing Wizard software. Last, a completed design can be
converted to a PROM programming file for implementation in an FPGA.
The NeoCad software is deterministic, have 100 weighting tables which vary
the approach the software takes -- don't really know what this means. :)
It is deterministic however, which means if you find a table number that
works for a design, you should use the same number when making changes.
My experience with this tool has been consistantly good, and in every way
superior to the toolset I have been using from Xilinx. In one particular
design, I spent a week attempting to place and route with Xilinx apr with
no success. Sent this design to NeoCad and they routed it in 15 minutes !!!
All of the NeoCad software is encapsulated in individual x-window wrappers,
but these tend to be little more than a graphical way to set the command line
options. They mainly help early on in getting familiar with the options
available, but I find these are swiftly replaced with appropriate "make"
files. The graphical editor for the FPGA designs is very intuitive and fast,
an excellent replacement for the Xilinx xde. Occasionally, the editor will
lose some wires (graphically) and you will have to refresh to get it repainted
on the screen. This is about the only bug I've stumbled on.
My particular needs are mainly focussed on the ability to fix the pins of my
FPGA design, and successfully perform 100% place and route. I have used
Timing Wizard some, but not extensively, as most of my designs are slow
(8 Mhz). In my application, I have used this tool in conjunction with the
Cadence Synergy product to develop a quick turn reprogrammable emulation
system for embedded processors. My goal is to write Verilog HDL, push
a button, and reprogram my emulation board with a new design. To this
purpose, the NeoCad place and route software performs quite well.
The EDIF reader supplied by NeoCad is fairly limited, not handling iterated
instances and it processes EDIF files quite slowly. The equivalent Xilinx
software processes the same EDIF file in less than 1/4 of the time, and
supports iterated instances. I believe this problem is related to the use
of wide busses...
The main problem I see with the NeoCad and similar tools is a lack of
integration of a "project". Ideally, a single tool should analyze and figure
out the necessary conversions from the EDIF file to the programming file,
asking the user just once what target to use. Instead, there are a series
of executables with a series of intermediate files, and numerous options
which mean little or nothing to the user except in purely empirical terms.
The place and route tool has 100 cost tables for tackling a design; a little
intelligence on the part of an integrated tool could remember which one works
and try to make smart guesses. Leaving it to the user with no information
about what each cost table means is pointless. Definitely an opportunity for
improvement.
- Robert L. Hoffman
Motorola
( ESNUG 178 Item 5 ) ---------------------------------------------- [2/93]
From: baker@mer-mail.ctron.com (Lauren Baker)
Subject: Suggestions on Synthetic Library Cache Setup and Usage?
John, has anyone explored the use and setup of the cache for the synthetic
libraries? We only have the basic DesignWare libraries, and currently every
user has their own cache. Often times different engineers may be compiling
a single design as a joint effort -- we don't use logins per chip.
Is there much to be gained by using a general cache? I have looked briefly
at Chapter 4 of the DesignWare Databook, and would like some advice whether
we should try to set something up. If we use a general cache, how should
we handle write/delete situations? Is there ever a problem that a design
doesn't use the best possible library, because a non-optimal one is already
cache'd? Any advice, suggestions, pointers would be appreciated.
- Lauren Baker
Cabletron Systems
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