During the DAC 5-CEO's-Act-Like-Professional-Wrestlers panel, Joe Costello
(CEO of Cadence) blurted: "We're stuck in a fixed-pie model. Have you seen
three big dogs hovering over one bowl of dog food? It's not a pretty
picture." Inspired by Aart De Geus's (CEO of Synopsys) flip reply of: "If
you think of yourself as a dog, you deserve dog food!", I'm starting a dog
food drive for Joe Costello! Mail your cans of dog food to "P.O. Box 6222,
Holliston, MA 01746-6222" or print this, mark how much & what you want
bought with a check to pay for it and I'll personally buy & deliver it to
Cadence Chelmsford in August. (I believe a good joke is worth the hassle!)
CANNED DOG FOOD: DRY DOG FOOD:
__ Alpo "Chunky Lamb" $2.00/3 Cans __ Purina Dog Chow $6.00/10 lb bag
__ Mighty Dog "Chicken" $3.00/5 Cans __ Kibbles'N Bits $11.00/20 lb bag
__ generic horsemeat $2.00/5 Cans __ generic beef $7.00/25 lb bag
__ Ken-L Ration "Beef" $1.00/3 Cans __ Gravy Train $9.00/20 lb bag
__ Skippy "Smoky Beef" $1.00/2 Cans __ Pedigree "Lamb" $12.00/22 lb bag
Clearly hand print how you want to be listed on Joe's "BON APPETIT!" card:
NAME (or "Anonymous"):___________________________________
COMPANY (or "Anonymous"):___________________________________
All money will be to buy dog food; what Cadence Chelmsford doesn't take will
be donated to the Framingham Humane Society.
:^) - John Cooley
the ESNUG guy
( ESNUG 221 Item 1 ) ---------------------------------------------- [7/95]
Subject: (ESNUG 220 #7) What's The Real Scoop On Synopsys & Solaris 2 ?
>Synopsys documentation claims that Synopsys should run fine on Solaris 2.
>Does anyone know different? Also what about Cadence, IKOS, Motive, etc?
>The reason I ask is that instead of purchasing a bunch more Sparc 20s for
>the new guys we're hiring for ASIC & FPGA development, I'd like to buy a
>couple of 4 processor boxes from Sun and connect through X-Windows Server
>S/W from our PCs. However, this is only viable using Solaris 2.
From: dblack@ink.apple.com (David C. Black)
I've been using Verilog Turbo (9404) & Synopsys 3.3a on a Sparc20 HyperSparc
running Solaris 2.4 for several months without a hitch in the EDA tool area.
(In fact there is an obscure Synopsys bug on another platform/OS that does
not show up on the Solaris version.) My only problems were getting Solaris
correctly installed and learning the new system administrative aspects. (I'm
my own admin.) Compiling GNU tools is also a challenge. None of this is
related to the EDA tools in any way.
Suggestion: Get Unison Labs' Load Balancer. It can direct different jobs to
different machines (arch & OS versions) automatically. Thus if one tool
works correctly only on a particular host or OS, you can setup load balancer
to automatically direct the job to that machine or group.
- David C. Black
Apple Computer
---- ---- ---- ---- ---- ----
From: jww@cadence.com (John Willoughby)
Cadence software is supported on Solaris (also Sun OS, IBM and HP-UX). I
don't know about Ikos or Motive.
- John Willoughby
Cadence Design Systems
---- ---- ---- ---- ---- ----
From: stokes@cmc.ca (Peter Stokes)
In the Design Framework II area of Cadence tools, Cadence is over 2 years
late in getting a Solaris 2 version. This is based on their never-ending
promises and then non-delivery. This could be Sun's fault, Cadence's fault
or both, I don't know. The last I heard was that it was a for-sure for
Cadence 9404 and then when 9404 was allegedly (I never had the chance to
see it) released for Solaris 2. (BTW, it was the last port and apparently
shipped to customers in calendar Q295, it was half-baked in that not all
Framework II products had been ported.) I'd say Cadence is still at a V0.9
on a Solaris 2 port. And the V1.0 of it _might_ be one to avoid. I'm not
revisiting the Cadence Design Framework II on Solaris 2 option until 1996.
- Peter A. Stokes
Canadian Microelectronics Corporation
[ Editor's Note: Peter founded comp.cad.cadence some years ago. - John ]
---- ---- ---- ---- ---- ----
From: gunes@jadeite.Eng.Sun.COM (Gunes Aybay)
John,
I have been using Synopsys on SS10 and SS20 machines with SuperSPARC and
HyperSPARC processors running Solaris 2.3 and 2.4 for more than a year
without any problems. Uniprocessor performance under Solaris 2.4 is slightly
better than uniprocessor performance under SunOS 4.1.3, however, for MP,
you should definitely use Solaris.
- Gunes Aybay
SUN Microsystems
( ESNUG 221 Item 2 ) ---------------------------------------------- [7/95]
Subject: (ESNUG 220 #5) Size Dependant Hierarchical Timing Bug (3.1b & 3.2b)
>I have timing report from a design, showing a 44.12ns path. I move up a
>level in the hierarchy, so the previous design is now an instance named
>"cntl" in this upper design. Now the *same* path now shows 214.02ns delay!
>It appears that this bug *only* occurs if you have a non-default driver on
>your input ports (i.e., if you leave it with the default "infinite" drivers,
>everything works). It doesn't matter if the path uses the clock or not.
From: sgolson@trilobyte.com (Steve Golson)
Further developments show this has nothing to do with hierarchical designs.
I see the problem on a single design. Run report_timing and see a path with
20ns delay, then put a non-inifinite drive on the clock pin with
"set_driving_cell" and report_timing shows 210ns delay.
- Steve Golson
Trilobyte Systems
( ESNUG 221 Item 3 ) ---------------------------------------------- [7/95]
Subject: (ESNUG 220 #1) Weird Asynch Pins In Xilinx VSS Library
>I found it odd that there are 2 asynchronous pins each: GSR & CLR for cell
>FDCE, GSR & PRE for cell FDPE in the Xilinx xc4000_FTGS.vhd of XACT5.1 for
>simulation of VSS. Has anyone found problems with these cells?
From: mjm@hpqt0326.sqf.hp.com (Murdo McKissock)
Dear John, I've that problem too. It's nice to know I'm not alone!
I have not succeeded in using the VSS simulation libraries for synthesis,
because the Xilinx synthesis libraries omit the GSR pin. For now I'm using
liban to build separate Xilinx VHDL libraries for synthesis only.
Unsatisfactory as it means editing the VHDL RTL code between simulation and
synthesis. (Personally, I like the 2 asynchronous pins. After all this is
how the cell behaves.) The Xilinx documentation assumes users will leave
global reset out of the RTL code, but I for one need to include it in
pre-synthesis VHDL code.
There should be a single VHDL package which provides synthesizable component
declarations for all the Xilinx library components as well as simulation-only
models bracketed with translate_off directives. That may require adding the
GSR pin to the FPGA compiler synthesis libraries ...
- Murdo McKissock
Hewlett-Packard Scotland
---- ---- ---- ---- ---- ----
From: steve.sharp@xilinx.com (Steve Sharp)
Hi John,
The answer to this quite resonable question lies in the internal structure
of the Xilinx XC4000 devices. These devices have a "hidden" net called
"GSR" (Global Set/Reset) that connects to every flip flop in the device
(even I/O block flip flops). The GSR net is asserted on power-up, plus a
user can connect any chosen signal to it as well. This GSR connection is
made by instantiating a STARTUP symbol and connecting it's "GSR" pin to
the desired global reset signal. (In the v3.2 Xilinx Synopsys Interface
libraries you need to set a "dont_touch" attribute on the instantiated
STARTUP to prevent the compile process from removing it. In the v3.3 XSI
libraires the dont_touch attribute is already present on the STARTUP cell).
Using the GSR net allows local (often high fanout) connections to the CLR
or PRE pins to be removed, thereby freeing up a significant amount of
local routing resources. When the XNFPREP program detects local CLR or PRE
connections also connected to the GSR pin of a STARTUP symbol, it removes
the local connections since they are redundant.
Since the GSR net is not available to the synthesis tools, there are no GSR
connections in the synthesis library (just CLR or PRE pins as appropriate.)
The VSS simulation libraires have both asynchronous pins because there will
be connections to both after place and route.
The XNF2VSS back annotation program will add a net called "GSR" to the
post-route netlist if the user does not use a STARTUP symbol to specify which
signal should be connected to the internal GSR net in the chip. This port
should be toggled (active high) at the beginning of the simulation to get
all registers into their power-up state. If the user did use STARTUP to
specify a GSR connection, that signal will be connected to the GSR pins of
all flip flop cells in the post-route netlist.
Local reset or preset behavoir of selected subsets of registers can still
be specified in the code behavior and will be synthesized using the local
CLR or PRE pins on the specified registers. (Just remember that the GSR
net resets or sets EVERY register in the chip).
Note: for XC5200 designs, the same concept applies except that the registers
only have CLR connections and the internal global signal is called "GR" (for
Global Reset). Likewise, the STARTUP cell has a GR pin instead of GSR.
Using the GSR net where possible can improve routability of Xilinx XC4000
(and XC5200) designs. We encourage users to take advantage of it.
- Steve Sharp
Xilinx, Inc.
( ESNUG 221 Item 4 ) ---------------------------------------------- [7/95]
Subject: (ESNUG 220 #2) Raising A DesignWare Module Through Hierarchy
>Is there a way to move a module that is N levels deep in the hierarchy up to
>the top level & have Synopsys create the appropriate port lists through all
>the intermediate levels? We are having a particular problem with the PCI
>DesignWare, where the I/O module is instantiated by DesignWare which is
>instantiated by our application module which is instantiated by the top
>level. The I/O module would really like to be at the top level. Ideas?
From: vvallet@vnet.ibm.com (Vincent Vallet)
John, there sure is a way to move a module deeply nested in a module
hierarchy. Here's the methodology I used once for such a case. Let's assume
a module named TOP which contains a module named A. A in turn contains B
which contains C, D and I/O. The problem is to move the IO module direcly
below TOP along with A.
1) with B as current design, first you should group all what is not IO.
If the I/O design is a cell named IO_cell in design B, this gives :
current_design B
group find( cell ) -except IO_cell -cell_name "Z_cell" -design_name "Z"
The result is that the design B contains now only 2 cells : the I/O
design plus a cell containing the rest of B.
2) then with A as current design, ungroup B. If B_cell is the name of B in
A, this gives :
current_design A
ungroup B_cell -prefix ""
The result is that you moved I/O from B to A. The rest of B is now in a
design called "Z".
3) to continue to move the I/O design to the TOP design you just have to
repeat the steps (1) and (2) one more time :
current_design A
group find( cell ) -except IO_cell -cell_name "Y_cell" -design_name "Y"
current_design TOP
ungroup A_cell -prefix ""
That's it. The drawback is that, by moving the I/O design instance this way
you can eventually rename some design ports. Also the A and B design are
changed in the Z and Y designs (or whatever the new names you entered).
- Vincent Vallet
IBM
( ESNUG 221 Item 5 ) ---------------------------------------------- [7/95]
From: biswal@india.ti.com (Krutibas Biswal)
Subject: DB2EDDM Chokes When Number Of Nets In Region Is High
John,
Most of the customers I support use Synopsys as the front end synthesis tool
and they translate to Mentor for ATPG and Simulation. All of them use SIFF
to translate to Mentor (not thru EDIF->ENWRITE of Mentor).
Synopsys supplies DB2EDDM as part of the SIFF software, which is a schematic
translator. When I use DB2EDDM for a design which has feedthroughs or
shorted nets, DB2EDDM is expected to put a NETCON in the EDDM schematic that
it creates. I have a netcon symbol in the ".sdb" symbol lib that I use to
create schematic. I have a "-NETCON" entry in the "library.map" file used
by DB2EDDM. It works properly when the designs having feedthroughs etc are
small, but fails when the congestion is high, i.e. number of nets in
that region is large. DB2EDDM gives :
"(warning) Unable to fix all feedthroughs on sheet <XXX> of design <YYY>."
Any idea as to how to fix this problem ??
- Krutibas Biswal
Texas Instruments (India)
( ESNUG 221 Networking Section ) ---------------------------------- [7/95]
Cupertino, CA - Need 1 perm. Senior Timing Analysis/Synopsys-Verilog person
to lead support on CPU project. Pls, No Headhunters! "kamalesh@apple.com"
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