Editor's Note: I'd like to apologize for not puting out ESNUG for the past
6 weeks but I've had four major conferences (Design SuperCon/SNUG/OVI/VIUF)
to attend plus I just got an engagement ring for my girlfriend (probably
meaning we're getting married) plus I put together and ran a major ESDA
Shootout at Design SuperCon plus... Oh, yea! -- I do run a business, too.
Also, upon getting back I found my landlord had "Aart" & "Harvey" (the two
goats named after the CEO and Chairman of Synopsys) in his truck and was
going to bring them to the slaughter house! "I'm gonna have me some goat
stew!", said my landlord. For quite some time now, "Harvey" figured out
how to jump out of the corral and would eat the X-mas trees in our back
yard. ("Aart" couldn't figure out how to get out of the corral.) "Harvey"
got bored with eating pine trees and decided to eat the bark off of (and
thus killing) two 20 year old peach trees instead. To boot, with all the
snow piled up, even "Aart" could jump the corral fence and they were both
caught eating grape vines! Now the landord says I got 2 days to find a new
home for the goats "or they're going to be in my freezer." Yikes!
- John Cooley
the ESNUG guy
( ESNUG 234 Item 1 ) ---------------------------------------------- [3/96]
From: oren@waterloo.hp.com (Oren Rubinstein)
Subject: BUG w/ set_input_delay & set_output_delay w/ real & virtual clocks
Hello, John.
I just discovered a pretty fundamental bug in the way Design Compiler v3.3b
treats the delays that are relative to virtual clocks. Namely, a
"set_input_delay -min" relative to a real clock (port) will override a
"set_input_delay -max" relative to a virtual clock. (The same applies to
set_output_delay with "-min" & "-max" between real & virtual clocks.)
The result is that you get a design *with* violations, while Synopsys thinks
and tells you there are none!!!
Synopsys script:
create_clock CLK -period 15
set_drive 0 CLK
set_dont_touch_network CLK
create_clock -name fake_clk -period 15
set_input_delay 3 -max -clock CLK I1 /* #1 */
set_input_delay 14 -max -clock fake_clk -add_delay I1 /* #2 */
set_input_delay 1 -min -clock CLK I1 /* #3 overrides #2 !!! */
set_output_delay 13 -max -clock fake_clk O1 /* #4 */
set_output_delay -1 -min -clock CLK O1 /* #5 overrides #4 !!! */
Result of report_port:
Input Delay
Min Max Related Max
Input Port Rise Fall Rise Fall Clock Fanout
---------------------------------------------------------------
CLK -- -- -- -- -- --
I1 1.00 1.00 3.00 3.00 CLK --
^ ^
| |
these should be 14.00 not 3.00 !! -----------
Output Delay
Min Max Related Fanout
Output Port Rise Fall Rise Fall Clock Load
---------------------------------------------------------------
O1 -1.00 -1.00 -- -- CLK 0.00
^ ^
| |
these should be 13.00 not "--" !! -----------
The workaround is to group the constraints by clocks. In the example above,
swapping #2/#3 and #4/#5 in the script fixed the problem.
- Oren Rubinstein
Hewlett-Packard (Canada) Ltd.
( ESNUG 234 Item 2 ) ---------------------------------------------- [3/96]
From: [ Not A Sun Employee ]
Subject: How To Temporarily Borrow Synopsys Keys From Within Your Company
John, Please keep me ANONYMOUS.
Suppose your company has both East coast and West coast offices like, for
example, Sun Microsystems. The people on the West coast won't get in
until at least 11:00 East coast time, and the people on the East coast
(officially) go home at 2:00 to 4:00 West coast time. The license keys are
running 24 hours/day, why not temporarily use the ones from the other office
while they aren't in the office?
For discussion's sake, let's assume you're an east coast engineer who wants
to use those west coast licenses. All you need is:
1) Network access to the machine running the license manager at the west
coast site -- just the ability to "ping" it directly is all you need.
2) A copy of the west coast site's license file. (It doesn't have to be
current, just not expired).
To make the west coast remote machine look local to your east coast site,
modify your /etc/hosts with the an entry which looks like the following:
123.12.1.12 sunwest
where 123.12.1.12 is the "dotted quad" of the remote license server, and
"sunwest" is the name of the machine in the "SERVER" line in the of the
copied license file. You can get this number by "telnet"ing to the west
coast remote machine.
If your site supports network aliases then you can modify /etc/aliases with:
sunwest: sunwest.sun.com
Where "sunwest.sun.com" is the full name of the remote west coast license
server. On a local network you may not need the ".sun.com" portion.
To test from the east coast, do the following:
>/usr/etc/ping sunwest
and if you get "sunwest is alive" you are done.
Now, setup your environment for Synopsys as usual, to your current favorite
version of Synopsys, then do the following:
setenv SYNOPSYS_KEY_FILE /tools/synopsys/license/key.westcoast
or
setenv LM_LICENSE_FILE /tools/synopsys/license/key.westcoast
Either will work. The path must be explicit, or the full path to the license
file from the other site on YOUR machines. This will override your license
file, and suddenly you will be using the license from the west coast.
Note, the "version" in the remote key file must be at least the version you
are running. You can't run 3.4 with a 3.3 license file.
Questions: IS THIS LEGAL?!!
Yes. As long as the license agreement says "Your company" and not "This
site, Your company" it is legal. You still have a set number of licenses,
you are just using them more effectively. Remember, this is a FEATURE of
FlexLM, not a bug. Also, some license agreements have things written into
them which expressly forbid doing this (Cadence Verilog is one of them).
WILL THIS WORK WITH TOOLS OTHER THAN SYNOPSYS?
Yes. Just modify LM_LICENSE_FILE to point to the correct license file for
the correct tool after setting up your environment to run it.
WILL I GET A PERFORMANCE HIT?
No. Traffic to the license server is very low, and you will be running
your local version of Synopsys. If the link to the west coast goes
down Synopsys will suspend execution until it comes back though.
Also, remember that you will only have these licenses *temporarily* -- when
the west coast "wakes up" and finds all their licences being used, they'll
probably unilaterally kill your processes without warning!
- [ Not A Sun Employee ]
( ESNUG 234 Item 3 ) ---------------------------------------------- [3/96]
From: cliffc@europa.com (Cliff Cummings)
Subject: LMG-Synopsys EISA Source Model Bug
John -
I don't know how many of your ESNUG readers deal with Verilog system
simulation and Synopsys-LMG EISA Source Models, but those who do will benefit
greatly from the following bug information. The EISA Source Model
documentation is missing information regarding the eisapmaster command set.
The eisapmaster.txt file is missing the compare_data argument here:
mem_read (addr, size, byte_number, compare_data);
------------
io_read (addr, size, byte_number, compare_data);
------------
burst_read (addr, size, byte_number, compare_data, num_burst);
------------
continue_read (addr, size, byte_number, compare_data);
------------
Since these commands can be run from an external command file, they are not
checked at compile time but give syntax errors at run time. The syntax
errors point to the offending command but only report "Syntax Error" with no
additional details concerning the error.
Unfortunately, we lost a couple of days due to this problem. The first
command in our command file was a read_mem command, which gave a syntax
error. We checked the documentation which indicated that the command was
correct as written. We then tried replacing the mem_read command with an
io_read command, yielding the same result.
I finally spent a few hours looking over the EISA source-model Verilog code
(which is translated from VHDL and extremely difficult to follow), found the
command tasks and noted that four of the 12 command tasks had extra
un-documented arguments. Adding the compare_data arguments to the above
commands fixed the syntax errors. Most nasty!! LMG is aware of the problem
and will be correcting the documentation in the future (date unknown).
Hope this saves somebody some wailing and gnashing of teeth ;-)
- Cliff Cummings
(now on my own instead of at "Qualis Design")
( ESNUG 234 Item 4 ) ---------------------------------------------- [3/96]
From: seahuh@sea.ericsson.se (Hartmut Huber)
Subject: Not ALL VHDL Is Created Equal: Synopsys/Leapfrog Library Issues
Hi John!
We are just starting an ASIC design. Setting up the environment, we found
out, that our ASIC vendor (TI) uses both the Synopsys IEEE (etc.) libraries
and Leapfrog's (we are using Cadence Leapfrog for simulation). Simulation
only modules use the Leapfrog libraries but synthesizable modules use it too.
But, when it comes to synthesis, Synopsys' libraries have to be used instead.
Now, it seems just to be impossible to use the same set of libraries both for
synthesis and simulation. Since that libraries and modules have are not new,
it seems odd, that nobody before was as strict as we about that. Maybe it's
not an issue at all? (Synopsys, Inc. told us to use the same set but could
give no reason for that!) After all, both sets of libraries have the same
functionality (IEEE & some more "standard" libs) and SHOULD be exchangeable.
Does anyone know what's really going on and how to handle this?
- Hartmut Huber
Ericsson Schrack
( ESNUG 234 Item 5 ) ---------------------------------------------- [3/96]
From: miller@symbol.com (Wayne Miller)
Subject: What's The Non-Propaganda Story On Behavioral Compiler?
John,
I'm looking for information / real user testimony on ESNUG on Behavioral
Compiler. I am also interested in the use model for DesignWare. We have
been doing design for several years and have only been using the "free" DW
components. Now with Behavioral Compiler, my Synopsys sales rep is really
pushing DesignWare, saying that without it BC can't work its magic. (The
only facts I can distill from my AE and the databooks is that I can't design
pipelined arithmetic without DW.) He is also saying that in our industry,
there is usually a DesignWare seat for every Design Compiler seat, which I
found hard to believe.
- Wayne Miller
Symbol Technologies, Inc.
[ Editor's Note: As always, if you wish to be anonymous in replying to any
ESNUG issue, just say so in your e-mail and I'll honor it! - John ]
( ESNUG 234 Networking Section ) ---------------------------------- [3/96]
Dublin, Ireland - 3Com Seeks ASIC/Hardware Design Engineers for Lan Switching
/ATM applications, No Agencies or Headhunters! "Vincent_Gavin@3Mail.3Com.Com"
Yorba Linda, CA - engineer w/ 2 weeks Verilog/Synopsys experience seeks FPGA
work; "Miracle Man" from SuperCon ESDA Shootout. "bpainter@ix.netcom.com"
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