> AVANT! WINS CONTRACT FOR MORE THAN $50 MILLION
>
> SUNNYVALE, Calif.--July 22, 1996 -- Avant! Corporation (Nasdaq:AVNT)
> today announced the receipt of a contract valued at more than $50
> million from a leading worldwide electronics company. The contract
> is believed to be the largest product purchase contract ever awarded
> to an EDA software supplier. ... The customer, who requested that the
> company not be named due to the size of the contract, said, "After...
When a user forwarded this to me, I immediately called a Cadence Spectrum
Services friend (OK, so I'm cavorting with the enemy) to have some fun
harrassing him about this.
CDS buddy: "What? You fell for that hoax? They just made that up as a
PR stunt! That's why they can't name the 'customer' !!!"
Me: "Are you kidding? They're a public company! The SEC would be
down on them like a ton of bricks if it was a lie."
CDS buddy: "That would be minor compared to what they stole... but I won't
go into that again... Oh, yea, I just heard that they're
now performing occult ceremonies at Avant! board meetings."
Me: "Don't you guys ever stop!!! ... I'll bet you a dollar
that there's something to this Avant! sale. Bet?"
CDS buddy: "Yes! -- but only if it's for an American dollar. That Hong
Kong dollar you gave me last time you lost didn't cut it."
So now I'm on a mission to find out the answer to the $50 million dollar
question -- and to get my Hong Kong dollar back. Any ideas anyone?
- John Cooley
the ESNUG guy
P.S. The deadline for the lawsuit survey has past. If you didn't reply
before now, don't bother. (I already have over 300 replies to tabulate!)
( ESNUG 244 Item 1 ) ---------------------------------------------- [7/96]
Subject: ( ESNUG 241 #7 243 #6) Lawyers Make Avant! Scarey; Going To Cascade
> I would reccomend you take a look at the Cascade tools to see if they fit
> your requirements - and no I don't work for them I just think they have a
> great tool set - there is also more likelihood of being able to complete
> your layout without the assistance of a lawyer ! - [ The Thin Man ]
From: David.Brantley@dalsemi.com (David Brantley)
John,
I whole-heartedly agree with "The Thin Man"'s critique of the Cascade tool
suite. We use Cascade tools here at Dallas Semi for both cell and block
level routing. We were using Cell Ensemble and Block Ensemble from Cadence
until Block Ensemble caused us to miss a market window on a part. It took
us 11 weeks to route a chip at the top level with Block Ensemble which could
have been done in 2 weeks manually (and eventually was done manually just to
finish the part).
We were "encouraged" by our CEO to find a tool which would work after this
fiasco. We held a benchmark/evaluation of top level routers. All vendors
were invited to participate. Only Mentor and Cascade made the "short" list.
We then contracted with both Mentor and Cascade to work with us on the next
chip to be done. Cascade easily won this portion of the evaluation in both
area and time to turn the chip.
We are also impressed with Cascade's technology independent cell libraries.
We are able to migrate designs from one technology to another with minimal
agony.
- David Brantley
Dallas Semiconductor
( ESNUG 244 Item 2 ) ---------------------------------------------- [7/96]
Subject: ( ESNUG 243 #8 ) VHDL Compiler Problems w/ Generics & Aggregates
>It gives the error:
>
> Error: Cannot determine type of the aggregate
> in routine top line 55 in file '...../ex.vhd'
> (This error can occur if an aggregate and a generic appear in the
> same component instantiation.) (HDL-206)
>
>When will Design/VHDL Compiler better support generics & aggregates?
From: Christopher Papademetrious <st92j0gw@dunx1.ocs.drexel.edu>
John,
We encountered the exact same thing. A slightly inelegant solution we used
was to assign a signal the correct aggregate of signals, then assign this
new signal as a whole to the port in the generic design. This was slightly
annoying, since our data-driven design had MANY ports of varying length,
with many sub-fields coming from different places, and required this kludge
everywhere to come together cleanly.
- Chris Papademetrious
Drexel University
---- ---- ---- ---- ---- ---- ----
From: "Serge.Martin" <serge.martin@cns.cnet.fr>
Hi John,
At CNET we too found it very frustrating to be limited by such "features".
What's worse is that most of the subset restrictions concerning structural
VHDL are not due to the synthesis process itself, but rather due to
limitations of ellaboration phase of Design_Compiler.
Rather than waiting for Synopsys to extend their synthesizable subsets, we
started using LEDA's HELIOS tool that allows such structural constructs to
be used for synthesis. HELIOS accepts VHDL (87 and 93) models expanding
features such as the use of generic parameters, the types of generic
parameters used, the bounds of generate statements, the use of full
configurations, and the use of complex expressions (including file I/O) to
initialize constants. (HELIOS generates an equivalent VHDL model that has
all of these features removed and is accepted by VHDL Compiler.)
- Serge MARTIN
FRANCE Telecom CNET Grenoble
---- ---- ---- ---- ---- ---- ----
[ Editor's Note: What follows is a related exchange of e-mails. - John ]
From: wyamamo@ibm.net (Wataru Yamamoto) to Kevin OBrien of LEDA:
> Mr. O'Brien, Does HELIOS convert the following description to Synopsys-
> VHDL-compiler-acceptable one?
>
> entity ex is
> port(p00: out std_logic_vector(0 to 8));
> end ex;
> architecture another_question of ex is
> begin
> p00(3 to 7) <= (others=>'0'); -- VHDL compiler hates this!(maybe)
> end another_question;
From: Kevin OBrien <kevin@leda.fr> to Yamamoto-san:
> Yamamoto-san, I ran your example through HELIOS. The results are:
>
> entity EX is
> port(signal P00 : out STD_LOGIC_VECTOR ( NATURAL range 0 to 8 ));
> end EX ;
> architecture ANOTHER_QUESTION of EX is
> begin
> P00 (NATURAL range 3 to 7 ) <= (3 to 7 => '0' );
> end ANOTHER_QUESTION ;
From: wyamamo@ibm.net (Wataru Yamamoto) to Kevin OBrien of LEDA:
> The above is not acceptable to Synopsys. :^( I expected the following,
> which is acceptable:
>
> architecture ANOTHER_QUESTION of EX is
> begin
> P00 (3) <= '0';
> P00 (4) <= '0';
> P00 (5) <= '0';
> P00 (6) <= '0';
> P00 (7) <= '0';
> end ANOTHER_QUESTION ;
From: Kevin OBrien <kevin@leda.fr> to Yamamoto-san:
You're beginning to touch on a very sensitive subject in VHDL circles: what
constitutes the synthesizable VHDL subset. The IEEE is currently in the
process of defining the syntax and semantics of such a subset and until such
time as they do, we will always have problems like the one you mention.
Each synthesis tool has many different idiosynchrasies. HELIOS was designed
as an "elaboration tool for synthesis", not as an "elaboration tool for
synthesis with Synopsys". 99% of the time this is the same thing, but as you
pointed out, there are always exceptions.
The difference between the result generated by HELIOS and that accepted by
VHDL Compiler for your example is very small and such differences could be
removed quite easily. It is not too difficult to envisage a -s option added
to HELIOS for Synopsys-specific elaboration to perform such transformations.
This would necessitate a small amount of development by us. As all such
development is based on user demands, if there is a big enough demand for
such an option, we'll develop it!
- Kevin O'Brien
LEDA
( ESNUG 244 Item 3 ) ---------------------------------------------- [7/96]
From: "Russell Ray" <rray@msai.mea.com>
Subject: The Best Way I've Found To Synthesize ROMs Using Synopsys
John,
I've been investigating synthesizing ROMs further and have found some
interesting facts. Yes, big ROMs are not nice in Synthesis. They take a
large amount of time to sythesize and routing can be very difficult in the
dense area produced.
However, ROMs are not yet available in the process we are targeting so we
still had to press on. I found that using a PLA input for ROM code gave the
fastest and smallest design (for my library of course). The only constraint
was "set_max_area = 0". When I tried to force a timing constraint my area
blew up and the timing was never met. By only setting the area I was able
to get the smallest and fastest implementation. We also tried large "case"
statements but they always came in slower than the PLA. We also tried to
optimize the PLA terms before passing to Synopsys. This also produced larger
and slower ROMs than giving it all of the terms.
- Russell Ray
Mitsubishi Semiconductor America, Inc.
( ESNUG 244 Item 4 ) ---------------------------------------------- [7/96]
Subject: ( ESNUG 242 #4 243 #1) Will Trade My Secret Switches For Yours!
> I look forward to hearing what others find while checking out some of
> those other undocumented commands!
From: Neil Hastie <hastie@isti.fr>
John,
There is nothing very secret about the existance of synopsys switches. All
an inveterate hacker needs to do is pass the dc_shell_exec executable through
the UNIX "strings" command and "grep" for a suitable result. For example,
the following command gives an interesting output listing all compiler
directives hidden or otherwise:
strings -a SYNOPSYS_PATH/dc_shell_exec | grep compile_
...also useful for hunting error messages, etc.
- Neil Hastie
International Supercomputing Technology Institute, France
---- ---- ---- ---- ---- ---- ----
From: Shannon Hill <hill@synnet.com>
John:
Here are all the compile_* strings I found in the design_compiler executable.
Maybe we could start a contest to see who could figure them all out!
(Synopsys employees could contribute, but certainly couldn't claim any
the prizes!)
- Shannon Hill
3COM
P.S. The one I want to know more about is "compile_faster" !!!
compile_assume_fully_decoded_three_state_busses
compile_assume_fully_decoded_tristate_busses
compile_benchmark
compile_characterize_black_boxes
compile_clean_inverters
compile_cost_inverter_removal
compile_cost_vector
compile_create_mux_op_hierarchy
compile_default_critical_range
compile_default_input_transition
compile_disable_area_opt_during_inplace_opt
compile_disable_hierarchical_inverter_opt
compile_dont_touch_annotated_cell_during_inplace_opt
compile_drc_cost_function_vector
compile_enable_master_slave_inference
compile_faster
compile_fix_multiple_port_nets
compile_flags string too long
compile_force_local_dont_care
compile_ignore_area_during_inplace_opt
compile_ignore_footprint_during_inplace_opt
compile_implementation_selection
compile_inplace_changed_list_file_name
compile_instance_name_prefix
compile_instance_name_suffix
compile_iterative_area_seqmap
compile_multiple_port_isolation_logic
compile_mux_mapping
compile_mux_no_boundary_optimization
compile_mux_ungroup_min_data
compile_negative_logic_methodology
compile_no_new_cells_at_top_level
compile_ok_to_buffer_during_inplace_opt
compile_optimization_cost_function_vector
compile_power_analysis_effort
compile_preserve_subdesign_interfaces
compile_preserve_sync_resets
compile_prioritize_design_rule_cost
compile_propagate_unconnects_from_subdesign_inputs
compile_remove_inverter_opt
compile_resyn_duplicate_logic
compile_size_up
compile_smart_multiple_port_fixing
compile_test
compile_test_design_naming_style
compile_update_annotated_delays_during_inplace_opt
compile_use_fast_delay_mode
compile_use_fast_sequential_mode
compile_use_low_timing_effort
compile_verify
fpga_compiler_fpga_only_override
library_compiler_version
lockup_by_test_compiler
optimize_reg_skip_compile
prepare_design_for_compile
report_compile_options
test_compile
test_test_compiler
use_fsm_compiler
( ESNUG 244 Item 5 ) ---------------------------------------------- [7/96]
Subject: (ESNUG 240 #7 242 #6 243 #4) Simulators Giving Frustrating X's
> On the subject of X's in your simulation... About 4 years ago several
> of us discovered this, and it took us a while to convince Synopsys that
> this was a problem with "synthesis and then gate-level simulation
> methodology". Synopsys wrote up a very nice App note that they should be
> handing out to every customer. However, the conclusion was that there is
> nothing wrong with the circuit and it will work perfectly fine, but that
> the problem is with simulation (and as was said before maybe the simulation
> vendors will take note and improve the simulators).
From: Steve Hwang <steveh@8x8.com>
John,
The simulation problem of 'X' propagation is due to the cell definition
of all the MUX cells. If users check their simulation library cell MUX,
it must be built with the simulator primitive ("and", "or", "not" ...).
To avoid the 'X' propagation, users need to define their MUX cell by
using a UDP (User defined primitive table). Here is a Verilog version of
a MUX21:
primitive p_mux21 (q, data1, data0, dselect);
output q;
input data1, data0, dselect;
// FUNCTION : TWO TO ONE MULTIPLEXER
table
//data1 data0 dselect : q
0 0 ? : 0 ;
1 1 ? : 1 ;
0 ? 1 : 0 ;
1 ? 1 : 1 ;
? 0 0 : 0 ;
? 1 0 : 1 ;
endtable
endprimitive
Most simulators support some kind of defined table format, so their users
can define the definition of their own library cells.
- Steve Hwang
8x8 Corp.
( ESNUG 244 Item 6 ) ---------------------------------------------- [7/96]
From: Peter Kamphuis <kamphuis@hl.siemens.de>
Subject: Having Problems With Synopsys Online Documentation & WorldView 2.1
John,
Recently we've installed Synopsys 3.4b and when trying the online
documentation I noticed some odd behavior. I was wondering if somebody
else noticed the same.
Upon startup, the "Search->Collection" window pops up automatically after
the welcome page is displayed. How can I suppress this behavior? I tried
to change some Xresources but without any luck. I also noticed that after
running install_help there are still two entries "/doc_root/" in the
created Iview file. I assume one can set these similar to the paths used
for Synopsys 3.4a.
Another question I have is: does anyone have some tips on how to use the
printerConfig Xresource with WorldView 2.1? I would like to be able to
print, for example, two pages on one (using pl2ps and PSUtils) directly
from WorldView. Using only a filter didn't work, but using pl2ps and the
PSUtils on UNIX level did. For Synopsys 3.4a I used an UNIX script to
print, for example, the Quick Reference Guides as a little booklet.
- Peter Kamphuis
Siemens Semiconductor, Munich
( ESNUG 244 Item 7 ) ---------------------------------------------- [7/96]
From: "David C. Black" <dblack@ink.apple.com>
Subject: Behavioral Compiler v3.4b Mysteriously Disconnected A Useful Net?
John,
While compiling a top level module in Bahavioral_Compiler that merely
instantiated two lower level modules (that were previously compiled) produced
a weirdness. A control net that is definitely functional within the design
(pre-synthesis) was disconnected between the two modules (it's an output
from one, and an input to the other). The dangling input was then tied
HIGH!? +%#@!! :-(
One suggestion from my local Synopsys team is that some problems with
boundary_optimization have been seen. Anyone with any ideas?
- David Black
Apple Computer
( ESNUG 244 Item 8 ) ---------------------------------------------- [7/96]
From: wlenihan@ccgate.hac.com (Bill Lenihan)
Subject: Last Minute 'Supplemental Licensing Agreement' Causing Headaches
John:
I have a problem: we ordered Synopsys FPGA Compiler & Designware. At the
*last minute* Synopsys threw at us a 'supplemental licensing agreement'
involving Designware.
I read a copy of the agreement which I received from Synopsys' local sales
rep. Although I'm not a lawyer, the agreement seems like it is clearly in
our favor: from a software perspective, it is akin to company A (Synopsys)
selling software to company B (Hughes) and company A allowing their software,
not just to be used by company B TO CREATE their software, but also TO BE
PART OF company B's final delivered software (except in this case it is the
digital hardware equivalent). It also says that we can't sublicense or let
others besides us use the software (no problem, this is standard licensing
language).
The problem is that I can't get my FPGA Compiler (which is what I really
need, Designware is for the future) until we resolve this agreement issue.
It appears that this last minute 'supplemental licensing agreement' will get
hung up at 3 or 4 different other legal and/or contracts points within my
company before the CD-ROM even leaves Synopsys.
Have you seen this logistical problem before, and if so do you have any
suggestions for greasing the procurement process? Any arguments to convince
the Bean Counters that this is OK (aside from my argument/analogy in the 2nd
paragraph above)? Any help or direction you can give me is appreciated.
- Bill Lenihan
Hughes Aircraft Co.
( ESNUG 244 Networking Section ) ---------------------------------- [7/96]
Roseville, CA -- Hewlett-Packard seeks ASIC Engineer with at least 4 years
exper. w/ Verilog & Synopsys. No headhunters. "paulo@work.rose.hp.com"
West Coast -- Intel seeks MSEE or BSEE + 2 years exp. who knows Cadence
CELL3 or other IC P&R tools. No agencies. "hiren@ptdcs2.intel.com"
Scotts Valley, CA -- Sierra Imaging seeks an exp. VHDL/Synopsys ASIC designer
with imaging experience. Principles only. "sean@sierraimaging.com"
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