Editor's Note: Because of the demand from SNUG'98, I'm re-posting ESNUG
141 item 3, Lee Bradshaw's 5 year old article about creating your own
wire loading tables. (This came up in many discussions at last week's
SNUG'98.)
And before you ask, the answer is "Yes, even though this is 5 years old,
it still works in Synopsys!" (Some things never change (much!))
In republishing this ESNUG, I can't help but remember a character from
Greek mythology, Cassandra, a woman given the gift of prophecy with
the curse that even though what she said would be true, no one would
believe her. My prophecy, from hard earned experience doing consulting
gigs, is that even though tinkering with wire-load models may appear
to get you out of a design synthesis problem, what it also buys you is
extremely contentious arguements with your foundry because they just
won't accept designs made with customer created wire-load models.
I know you don't believe me. I've accepted that. Happy tinkering! :^)
- John Cooley
the ESNUG guy
( ESNUG 284 Item 1 ) ----------------------------------------------- [3/98]
From: LBradshaw@engineer.clemsonsc.NCR.COM (Lee Bradshaw)
Subject: ( ESNUG 141 #3) Creating Your Own Wire Loading Tables
NOTE: You DO NOT need the library compiler to make use of the following
information. 3.1 looks like it has much better support for physical layout
issues, but I believe the information here could help you avoid some
iterations between Synopsys and your layout tool.
This posting started with an awk script to generate custom wire loading
tables based on actual placement info with Synopsys 2.x. It evolved into a
more general purpose algorithm (presented below.)
Many vendors don't provide useful wire loading tables. I have seen several
tables that just give a linear slope for the top of the die and no tables
for anything smaller. You can use the wire loading table for a smaller die,
but this may still not be small enough for a closely placed block containing
1000 gates. The asic vendors generally want to overestimate capacitance.
Then they will not have to worry about placement (i.e. if you are happy with
the maximum speed using their wire loading tables, they will have no problem
placing and routing.) However, if you need more performance, you will need
better wire loading tables to feed synopsys, and you will have to be more
involved in layout.
The following example shows how to build your own wire loading tables. The
final few lines tell synopsys 3.0 to automatically pick the correct wire
loading table based on the number of gates being compiled. To make use of
this feature, you must have the wire loading models as the first library in
your link path. Comment these final lines (marked in the code) if you are
using pre-3.0 synopsys. If the number of gates crosses a boundary during
compilation, you will have to do an incremental compile to switch to the new
wire loading table.
dc_shell> read_lib wire_table.lib
/* lots of warnings and errors followed by... */
Library 'wire_table' read successfully
1
dc_shell> report_lib wire_table /* to see what happened */
dc_shell> write_lib wire_table
The final step in usage is to set the mode for hierarchical designs.
Before 3.0 you will use a command like:
set_wire_load "10k" -mode segmented
This command sets the wire loading model and specifies how to
handle hierarchy.
After 3.0 you can just use:
set_wire_load -mode segmented
You can also use this command to override the default table for 3.0 and
greater.
The mode can be either segmented or enclosed depending on whether you want
the wire segments that cross hierarchy levels to use stubs at each level, or
to do all computations based on the highest level the wire is in. The mode
could also be top, but then your synthesis at the low level and timing
analysis at the higher levels will not match.
The fudge factor is dependent on many things: how good a job of placement
and routing your tools do, whether your layout tools support timing
constraints, your performance in generating the physical hierarchy with a
floorplanner. Good placement algorithms, timing driven placement, and good
floorplanning should push this lower. If you have problems with some of
these areas, the fudge factor may need to be increased to handle your worst
case path. The wire loading tables will be over constraining most of the
design in order to provide enough constraints on the critical path.
Try expanding the table and getting the capacitance and length numbers from
your vendors. You can check your numbers against theirs by using
report_lib. Remember these tables are approximations. They can be more
accurate than some vendor supplied tables, but back-annotation data is even
better.
- Lee Bradshaw
NCR Corporation
/****************************************************************
/ File: wire_table.lib
/ Wire loading table example
/ Lee Bradshaw
/ 11 Dec 92
/
/ This library should be the first one in your link path.
/ Then synopsys (3.0+) will automatically use the different
/ size tables according to the number of gates being compiled.
/
/ WARNING: Designer or router must place the gates so that
/ they actually fit in an area of the estimated size.
/ Otherwise, the estimated loads will be too small, the
/ drivers will be too small, and the circuit will run
/ slower than estimated.
/
/ For hierarchical designs, use the command:
/
/ set_wire_load -mode segmented
/
/ EXAMPLE: Compiling a module that has 2000 gates,
/
/ Synopsys (3.0+) will automatically pick the table to use
/ for 2000 gates. If the gates are actually scattered in an
/ area for 10,000 gates, then the capacitance will be too
/ low. Use the following command to manually adjust in
/ this case.
/
/ set_wire_load "10k"
/
/ Modify the following parameters for different vendors(description below):
/ fudge
/ cap
/ length_10k
/ length_top
/
/ Cut and paste the areas starting with
/ length = length_x
/ wire_load("x") {
/ ...
/ }
/ to generate tables with different sizes. Also define any new
/ length_x values, and add x to automatic selection lines at the
/ end of the file.
/
/***************************************************************/
library ("wire_table") {
/* fudge = correction factor, routing, placement, etc. */
fudge = 1.0
/* cap = fudge * (metal1 + metal2) / 2, careful with 3-layer */
cap = fudge * (0.23 + 0.26) / 2.0;
/* length_top = the length of one side of a square die
length_10k = the length of one side of a block containing
10k gates */
length_10k = 4.5;
length_top = 15.0;
/* sqrt(5000/10000) = .71
sqrt(2000/10000) = .45
etc */
length_5k = length_10k * 0.71;
length_2k = length_10k * 0.45;
length_1k = length_10k * 0.32;
length_500 = length_10k * 0.22;
length = length_top;
wire_load("top") {
resistance : 0 ;
capacitance : cap ;
area : 0 ;
slope : length * .5 ;
fanout_length(1,length);
fanout_length(2,length * 1.5);
fanout_length(3,length * 2);
fanout_length(4,length * 2.25);
fanout_length(5,length * 2.5);
fanout_length(6,length * 2.75);
fanout_length(7,length * 3);
}
length = length_10k;
wire_load("10k") {
resistance : 0 ;
capacitance : cap ;
area : 0 ;
slope : length * .5 ;
fanout_length(1,length);
fanout_length(2,length * 1.5);
fanout_length(3,length * 2);
fanout_length(4,length * 2.25);
fanout_length(5,length * 2.5);
fanout_length(6,length * 2.75);
fanout_length(7,length * 3);
}
length = length_5k;
wire_load("5k") {
resistance : 0 ;
capacitance : cap ;
area : 0 ;
slope : length * .5 ;
fanout_length(1,length);
fanout_length(2,length * 1.5);
fanout_length(3,length * 2);
fanout_length(4,length * 2.25);
fanout_length(5,length * 2.5);
fanout_length(6,length * 2.75);
fanout_length(7,length * 3);
}
/* Comment these lines for synopsys before 3.0 */
default_wire_load : ("top");
wire_load_selection () {
wire_load_from_area ( 0, 5000, "5k");
wire_load_from_area (5000, 10000, "10k");
}
/* End comment for synopsys before 3.0 */
}
/* END OF WIRE LOADING EXAMPLE */
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