"It's because I was young. When you're young, you're supposed to do
stupid things, aren't you?"
- David Bishop of Kodak explaining a "mistake" he made in college
Editor's Note: On the weekend between the SNUG and OVI/VIUF conferences,
I got together with my old college lab partner, "NOP", (who lives in
Silicon Valley) and with David Bishop of Kodak (who remained an extra day
to get the "over Saturday" cheap airfares.) It being Saturday and the
three of us being engineers, we quite naturally went to San Francisco's
museum of science, (the "Exploritorium") and, as luck would have it, it
was a special day. It turns out every March 14th is considered "pi" day,
and 1:59 is the official time to celebrate. (March 14th... that's 3/14 at
1:59 ... 3.14159 ... get it?) It also turns out that 3/14 is Albert
Einstein's birthday. And it was at this gathering that David Bishop
suddenly "outed" himself (no, not *that* kind of "outing"!) he suddenly
confessed that while in college he had joined the "Pi Society" in which
he memorized "pi" to 100 digits to join! Dave was now finally home! :^)
"How does one celebrate 'pi' day, John?", you ask. Well, at 1:59 they had
all 20 of us stand around a circular bronze plaque in the floor dedicated
to "pi" and they had us walk around it 3.14 times. (ABC News even
videotaped us!) As we started walking around in front of the ABC
camera, I started chanting "3-.-1-4-1-5-9, Happy Birthday Einstein!"
(Of course, this not having been part of the "pi" celebration organizer's
plans, I found myself chanting it quite alone the whole 3.14 rotations.)
Dave & "NOP" pretended they didn't know me. At the end of the circular
walk, they served up pie (as in pumpkin, blueberry, apple) and, this being
my first "pi" celebration, I asked for and got cherry pie. (My parents
back in Vermont later said they saw/heard me for 7 seconds on TV in the
background of that story on the "ABC Evening News with Peter Jennings".)
At the end of that day, upon reflecting on the nerdiness of it all, I
made the mental note: "John, this was fun but when you return home,
perhaps it's time to get a life."
"3-.-1-4-1-5-9, Happy Birthday Einstein!" :^)
- John Cooley
the ESNUG guy
( ESNUG 285 Item 1 ) ----------------------------------------------- [4/3/98]
From: "Tom Harrington" <tharring@ford.com>
Subject: Design Compiler 98.02 "write_script" Writes Out Erroneous Code !
John,
We've been evaluating DC 98.02 here, and we've come across a problem
that may affect whether we can use this release.
Put simply: If you do a write_script in 98.02, you may get a script which
contains erroneous code. Reading this code back into dc_shell will then
cause errors. The worst offender we've seen so far is the following:
set_wire_load "SMALL" -library "udr180T155V45" -mode "enclosed" \
-selection_group "udr180T155V45" -library "udr180T155V45"
Astute readers will note that it's illegal to specify "-library" more
than once with a set_wire_load command, even if it's the same library.
If this is read back in to dc_shell, it correctly reports an Error.
This only seems to affect multi-pass compiles; it did not show up
in the first compile pass, but was present in subsequent passes.
We also saw several lines similar to the following:
set_input_delay 0 find(port,"MINS")
When read back in to dc_shell, you are of course warned not to specify
an input delay without an associated clock.
Synopsys has issued a STAR on this matter. So far I don't know of
a work-around.
- Tom Harrington
Ford Microelectronics
( ESNUG 285 Item 2 ) ----------------------------------------------- [4/3/98]
Subject: Whether Or Not Undertow (From Veritools) Can Draw Schematics
> "The other highlight was Summit, who was showing a Verilog simulator
> that had a live display of a psuedo-schematic representation of the
> netlist. This would have saved hours and hours and maybe even
> days while debugging [Project Names Deleted]. Someone alleged that
> Undertow could do something similar, which I will attemp to verify."
From: schop@veritools.com (Robert Schopmeyer)
John,
Yes, Undertow can draw a schematic from the Verilog, either for RTL or gate
type designs. This schematic can display the modules, and gates or source
code driving the outputs. Users can also display their Powermill,
Timemill, and VHDL signals from at VSS while at the same time they are
displaying VCS signals and schematics.
- Robert Schopmeyer
Veritools Inc.
( ESNUG 285 Item 3 ) ----------------------------------------------- [4/3/98]
From: comparin@poci.amis.com ( Erik Comparini )
Subject: Design Compiler Has Problems With Same Named VHDL Packages
Hi John,
What I am reporting here may not be new to a lot of users, but it is
certainly an annoyance. This problem has been reported to Synopsys by me
long ago, but so far nothing has been done. Here's the scoop:
VHDL has this cool thing called packages, where you can stuff a lot of
things that you use over and over again, among other things. The language
standard does support 2 or more different packages with the same name, as
long as they reside in different libraries.
Design Compiler is notorious for supporting the "synthesizable" sub-set of
VHDL, but it does weird things with constructs that it supposedly supports.
An example of that are packages. If you have 2 or more packages with the
same name, and you analyze them into different libraries, each one of these
libraries with different logical names, mapped to different physical
locations in your disk, when you analyze your design, DC will consider that
an error! Here is the message that it spits out when I do "analyze -f vhdl
finaln.vhd" from within DC:
Error: Could not find object component INV2. This error can occur if a
package (COMPONENTS) that exists in memory also exists in another
library referred to in a Library statement. This error can also
occur if the package uses synthesis_off/synthesis_on directives
around the object.
In my particular case, both packages are called COMPONENTS, so the first
part of the error message is what really applies here. Each one of my 2
packages contain component declarations of gates used in the design (one has
core gates, the other has memories), and that's why they're named that way.
The error message above is also returned when you vhdlan w/ -spc_elab.
This is not a disaster, but it sure does not help. All other tools that
support VHDL that I have come across so far don't have heartburn with
homonymous packages in different libraries, INCLUDING VSS!! In other words,
when you use vhdlan without any of the SPC switches, the analyzer likes it
and does what you'd expect.
Bottom line is that if you want to work around this problem in DC, you
have to use different package names, no matter where they live. This
is an unnecessary limitation, as far as I can tell. Will Synopsys wake
up to this one?
- Erik Comparini
AMI
( ESNUG 285 Item 4 ) ----------------------------------------------- [4/3/98]
Subject: Non-XOR Oriented Ways Of Generating Random Numbers
> How can you implement a random number generator?
>
> I remember thet it can be done with a shift register and XOR gates, but I
> forgot which bits to XOR for best results. The next possibility is with
> formula, but I can not remember them.
>
> - Simon Hribernik
> Metrel
From: nesterov@holo.ioffe.rssi.ru (Andrew V. Nesterov)
You can XOR, but it fails most of rigorous tests for randomness. Try a web
search on either Marsaglia or DIEHARD. Dr. Marsglia of FSU has written
several papers on the subject, some of them are accessible over the net.
Alternate approaches are with formulas like Multiply With Carry (MWC), Add
With Carry (AWC), Subtract With Borrow (SWB), Lagged Fibonacci (LFG) or any
of linear combinations of modulo M.
MWC: x(n) = A*x(n-1) + C mod M (upper bits are the new carry (C), lower
bits are the new pseudo-random number)
LFG: x(n) = x(n-s) op x(n-p) mod M (s > p > 0, op is either + or -)
AWC: x(n) = x(n-s) + x(n-p) + C mod M
SWB: x(n) = x(n-s) - x(n-p) - B mod M
For further reference take a look at:
http://www.taygeta.com/random.html
http://www.ncsa.uiuc.edu/Apps/SPRNG/www/paper/node1.html
ftp://stat.fsu.edu/pub/diehard
Hope it helps,
- Andrew V. Nesterov
Ioffe Phys. Techn. Institute Russia
( ESNUG 285 Item 5 ) ----------------------------------------------- [4/3/98]
Subject: (ESNUG 282 #3 283 #9) Anyone Using Summit/Mentor's Text->Graphics?
> What I want to know is this: Is anybody out there using the Summit
> tool, or any other tool, for real text to graphics conversion. Not just
> to capture the hierarchy of the design with a bunch of block diagrams, I
> mean real text to graphics, creating bubble diagrams from state machine
> code.
>
> - Byron Reams
> NCR Columbia, South Carolina
From: Jim Avant <javant@HomeWireless.com>
John,
Concerning Byron's question, we are currently evaluating Summit's Visual
HDL and it WILL create some pretty decent-looking schematics and bubble
diagrams from Verilog code. The state diagrams usually need some slight
clean-up work (moving text that ambiguously falls on 2 arcs). I doubt
that a generated diagram from an FSM with more than, say 2 dozen states
would be very readable at first but if you're willing to spend a little
clean-up time you could probably still get some pretty useful documentation.
Of course one could argue that state machines larger than that should be
broken up anyway but that wouldn't be me doing the arguing.
This is slightly off-subject, but in the past (at another company) I've
used the VeriBest tools to generate schematics and bubble diagrams which
it converted to Verilog code for me. After a couple of years of working
with them, the tool finally created some pretty decent code. Personally,
I like having the flexibility to enter a design in multiple ways.
Visual HDL seems to do as good a job here as VeriBest. But if you ask
me if I would pay for such a tool if the money were coming out of my own
pocket (or even out of the pocket of a small start-up company) I'd have
to say thanks but no thanks. However, if I could float a license or two
between 4 or more designers (who would actually use it), then I'd buy it.
Having said that, though, even if I had Visual HDL I would still enter
simple state machines as text and just use the tool to generate the
graphics. But for chip top-level block connectivity (instantiations
only), I would enter the design in the schematic editor.
These are my own experiences and personal opinions and I know that most
designers with my level of experience would just prefer to bang it out
in vi. So we'll just have to agree to disagree, OK?
- Jim Avant
Home Wireless Networks
---- ---- ---- ---- ---- ---- ----
From: cmv@ancor.com (Craig Verba)
John:
At Ancor Communications, all our previous ASIC designs were done using
entirely VHDL text.
Recently, we bought Summit's Visual HDL for VHDL with a Text-to-Graphics
options. I took a design from a previous ASIC, which is to be updated and
used in our next ASIC, and imported into our new Visual design structure
using Text-to-Graphics. I created a directory ( "lib" ) in my Visual
design area, copied my textual VHDL entity and architecture into
this directory, compiled the VHDL then clicked the Text-to-Graphics
(Flowchart) option. Visual then created a flow chart diagram(s) of the
process(es) in the design. Visual created actual decision boxes, action
boxes, case statement trees and properly labeled all boxes. Visual also
created the appropriate signal declaration and logical assertation
statement for any logic not covered by the flow charted processes.
When I clicked on Generate VHDL, the code Visual created from the flow
charts it created was exactly the same as my original text VHDL. Simulation
with the original test vectors also confirmed that Visual had created an
exact match to the original VHDL. Again, all I really needed to do
was "click" the proper option and Visual did all the rest.
I have talked to another engineer in out department who has successfully
created state diagrams using Text-to-Graphics. Depending on the the number
of processes or states a particular VHDL design has in it, the created
flowchart or state diagram may not be pretty to look at, but it can be
cleaned up using by using the diagram editor. I believe Summit is working
on making the Text-to-Graphic software more "artistically" inclined.
- Craig Verba
Ancor Communications
---- ---- ---- ---- ---- ---- ----
From: Jean-Bernard Veuthey <jbernard.veuthey@eiv.ch>
Hi, John,
I used successively SDS (Mentor), VisualHDL (Summit) and now Renoir to
describe VHDL designs.
Once you understand how one SW works, it is not a problem to use the other
ones. They are quite similar to use: graphical entry of the structure,
state machines, ... Just setup carefully the strucure of your files,
directories and libraries and chose the right packages. This is the main
challenge of those SW.
Visual has the advantage to include a simulator. But I had some problems
with the SDF file (VITAL backannotation). In a fiew hours (one or two),
the students I work with, are able to implement small designs. No very
large design experience (up to 5-6k gates).
For political and financial reasons, I'm using now Renoir. The user
interface is almost the same as Visual. The Simulator is QuickHDL (or
QuickHDLlite on PC). I noticed no major problems with the last version.
The version 3.0 seems to me a Beta release. Now it works better. I
developed designs up to 10-20 kgates.
In summary, you need almost no time to learn the user interface (intuitive).
Just be carefull with the setups. The big advantage is that you don't need
to write the whole structure of your design (automatically generated), and
when you change something in the structure, it's easier to propagate the
modifications through the design (graphically).
For large designs, the main problems will come from the synthesis tools!
That's another challenge.
- Jean-Bernard Veuthey
Ecole d'Ingenieurs du Valais Sion, Switzerland
---- ---- ---- ---- ---- ---- ----
From: verschue@eb.ele.tue.nl (Ad Verschueren)
John,
Check out our *freeware* 'Interactive Design & Simulation System' at
http://www.eb.ele.tue.nl/proj/idassfly.html :
- Interactive graphical/textual design entry
- Continuous simulation of the design *during entry*
- Fully retargettable (and synthesizable) (V)HDL generation
- Easy to learn/use (we use it in 1st trimester university courses)
- Handles complex designs like ATM switches or superscalar OOO processors
and
- It's freeware!
OK, we wrote it, so we are a bit biased - use it ourselves though (fun!)
Currently, only Compass VHDL checked to be synthesizable (but includes
generation of shell scripts for RAM/ROM macrocell generation and pad ring
creation - 'no errors, no warnings' from *our* Compass system).
Also it runs on bare bones PC only in an ancient (but extremely stable)
dialect of Smalltalk. Have fun!
- Ad C. Verschueren
Eindhoven University of Technology Eindhoven, Netherlands
( ESNUG 285 Item 6 ) ----------------------------------------------- [4/3/98]
Subject: (ESNUG 282 #10 283 #1) Formal Verification, Formality & Chrysalis
> 1) Language synthesis, while not rocket science, isn't trivial. To
> develop one from scratch isn't much fun. Would you write a
> completely new one, if you had the industry-standard version already
> available to you? (This is the basis of the Chrysalis complaint.
> Formality may use the same (or similar) code to do language
> synthesis as did DC, thus, errors introduced in the DC synthesis
> step will be replicated in the Formality synthesis step, and thus
> won't be caught. I don't know whether Synopsys used the same code
> or not.)
From: "Duncan M. (Hank) Walker" <walker@cs.tamu.edu>
John, I think the essential point here is that "low effort" synthesis is
likely to be more bug-free than the heavy-duty optimizations applied later.
Werner von Braun's "too dumb to fail" argument.
> 3) Equivalence checking algorithms: Sadly (or happily, depending on your
> perspective), the time/memory/whatever required for equivalence
> checking is proportional to the SIMILARITY between the designs - not
> on their size or the function they implement. For example, it is not
> hard to compare multipliers, if you know that they are multipliers
> (not buried in logic), and expecially if you know the algorithm they
> use. Similarity comes up in spades, if you try to compare FSMs which
> use a different state encoding (or, equivalently, in pipelined logic,
> if the synthesis tool has done extensive retiming & re-optimization).
> Again, there is no problem if you happen to pick the same encoding as
> DC (but how do you do that, if you are a separate vendor, and don't
> have hooks into DC?), or know how DC did the encoding.
From: "Duncan M. (Hank) Walker" <walker@cs.tamu.edu>
This is only true if you use structural information in your equivalence
checker, such as finding potentially equivalent nodes by random simulation,
recursive learning, etc. A pure functional approach, such as BDDs, depends
only on functional similarity, not structural similarity. Of course all
the really good verification tools, such as IBM Verity, use some structural
similarity to reduce the problem complexity. The author is implying that
algorithms that don't need similarity, e.g. model checkers, can't handle
big designs. True, but they can be used on pieces of the design.
- Duncan M. (Hank) Walker
Texas A&M University
---- ---- ---- ---- ---- ---- ----
From: "Anders Nordstrom" <andersn@nortel.ca>
John,
I have used both Chrysalis and Formality to do RTL to gate comparisons
on a 850k gate chip. Both tools had their successes and their
failures but I think that Chrysalis has a more mature tool without
going into technical details about algorithms. The Chrysalis tool
was available on the market long before Formality and I did pretty
much all work with Chrysalis.
One of the most critical issue I have with Formality is that it is
using Synopsys synthesis libraries. If there is a bug in the synthesis
library the resulting gatelevel netlist will not be functionally
equivalent to the RTL and you would not be able to find this with
Formality since your reference was incorrect.
Chrysalis uses the ASIC vendors library which is also the one used
for ASIC sign-off. If the synthesis library is different from the sign-
off library this will today only be found with Chrysalis.
I did find a bug in our vendors synthesis library. One type of flip
flop had an asynchroneous reset but it was modelled as a synchroneous
reset flip flop in the synthesis library. This bug would have been
pretty hard to find in the lab.
- Anders Nordstrom
Nortel Ottawa, Ontario
( ESNUG 285 Item 7 ) ----------------------------------------------- [4/3/98]
Subject: Nine Different VHDL-Based Text Editors That Run On Windows NT
> Can anybody recommend a text editor that works well w/ ModelSim on NT4.0?
> We would especially like to be able to compile and read back error
> messages from within the editor. Features like configurability, macros,
> and VHDL syntax highlight would also be good.
>
> - Jacob Nielsen
> Ernitec A/S Hoerkaer, Denmark
From: molenkam@cs.utwente.nl (Bert Molenkamp)
Try WinEdit at "http://www.windowware.com". You can compile from within
WinEdit, you can highlight the VHDL keywords, etc. You may use it for
evaluation for a month.
- Egbert Molenkamp
University of Twente Enschede, the Netherlands
---- ---- ---- ---- ---- ---- ----
From: "Pak Khong" <pak.khong@fujitsu.com.au>
I have found ED4W-HDL to be very good. It has all the features that you
mentioned above (compile and read back error messages from within the
editor include jump to the error line when doubling clicking the error
message, VHDL syntax highlight, automatic testbench generation, VHDL
models, etc) and works on NT4.0 as well. You can download an evaluation
version from www.silicon-systems.com.
- Pak Khong
Fujitsu Australia Limited
---- ---- ---- ---- ---- ---- ----
From: Malcolm Box <M.D.F.Box@nortel.co.uk>
Emacs. I use it and love it. Infinitely configurable, full programming
language, great VHDL highlighting and source templates. It will easily
hook up to the compiler and jump to error points.
http://www.cs.washington.edu/homes/voelker/ntemacs.html for more
- Malcolm Box
Nortel
---- ---- ---- ---- ---- ---- ----
From: "Byron Reams" <byron.reams@MCI2000.com>
For all you "vi" bigots out there, you might want to get vim (v5.0).
http://www.vim.org
One of the new features is color syntax highlighting and included in the
install package are files to handle verilog and VHDL syntax. One of the
links has Win32 binaries so no compiling is required...
Also, for those of you familiar with vim v4.6, this latest version has a GUI
interface and resizeable windows.
- Byron Reams
Intel
---- ---- ---- ---- ---- ---- ----
From: markg@vulcanasic.com (Mark Goodson)
We sell an HDL editor called Sledgehammer. It does pretty much everything
that you require and works with VHDL, Verilog and ABEL.
- Mark Goodson
Vulcan ASIC Ltd
---- ---- ---- ---- ---- ---- ----
From: tom@erinet.com (Tom Palermo)
Try UltraEdit by IDM. I've been using it for years with very good results.
It has syntax highlighting and source templates plus a lot of other advanced
editing features. I don't know if has the capability to jump to errors
since I compile on a Unix network but edit locally on my NT box. You can
get an eval copy at: http://www.idmcomp.com
I've also got the syntax highlighting setup for EDIF files, log & report
files, and other FPGA vendor specific files.
- Tom Palermo
Cincinnati Electronics
---- ---- ---- ---- ---- ---- ----
From: "Mehrban Jam" <jam@hpl.hp.com>
I use CodeWright from Premia. Besides syntax highlighting you can use it as
IDE with ModelSim. You can edit, run the compiler, and jump to error
locations all in one place in CodeWright.
- Mehrban Jam
Hewlett Packard Laboratories, Palo Alto, CA
---- ---- ---- ---- ---- ---- ----
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Sorry, got in on the thread a bit late. Please do visit:
http://www.saros.co.uk/
You will find a very nice editor called Turbowriter. A Free 30 day eval
license is available.
It is based around Codewright and has nice features like testbench harness
generation, component generation (for easy instantiation) and there are
templates based around two letter mnemonics. It will analyse your code to
find your named processes, variables, signals, etc. and stick them in a
navigation window so that you can move around real quick. Oh yes, it colour
codes, and hooks directly to Modelsim. Plus when you get an error report
from Modelsim, it'll take you to the offending line.
Try it, I think you will like it. I do, but I could be considered biased
as I just started work for Saros this week. :-)
- Stuart Clubb
Saros
---- ---- ---- ---- ---- ---- ----
From: "John Maher" <jmaher@silicon-systems.com>
Try visiting http://www.silicon-systems.com for a free 45 day trial of a
windows 3.1/NT VHDL/Verilog editor.
It provides: colorised keywords, automatic testbench generation, automatic
template expansion, dozens of free models which can be automatically
inserted at cursor, comment of selected area, and error tracking for
MODEL SIM (VSYSTEM from Model Tech)
New "Expert" release due very shortly, with more enhancements!
- John Maher
Silicon-Systems
---- ---- ---- ---- ---- ---- ----
> For emacs I have 19.34 on Win95, but I don't have a VHDL mode - is there
> one? How do you do the syntax highlight?
>
> - Evan Shattock
> Riverside Machines Ltd.
From: "Thomas D. Tessier" <tomt@hdl-design.com>
Yes, look on the links in http://www.vhdl.org.
Recently updated looks very slick but I am still using the one I customized
over a year ago. Can't let go of a good thing.
- Thomas D. Tessier
T2Design
---- ---- ---- ---- ---- ---- ----
From: Edwin Naroska <edwin@mira.e-technik.uni-dortmund.de>
You will find a vhdl-mode at
http://www.geocities.com/SiliconValley/Peaks/8287/
- Edwin Naroska
University of Dortmund Dortmund, Germany
( ESNUG 285 Item 8 ) ----------------------------------------------- [4/3/98]
From: Jean-Marc Allard <jm.allard@hol.fr>
Subject: Need Help With Synopsys In-Place Optimisation (IPO) Technique
John,
I want to fix design rule violations (max_capacitance and max transition)
on a backannoted design using synopsys IPO (in place optimisation). I only
want to allow cell swapping, from low drive to higher drive. I have about
100 violations and synopsys swaps about 1000 cells. I do not understand
why so many cells are swapped. I notice that few cells are replaced with
a lower drive cell. My script is the following:
compile_ignore_footprint_during_inplace_opt = TRUE
compile_ignore_area_during_inplace_opt = TRUE
compile_disable_area_opt_during_inplace_opt = TRUE
reoptimize_design_disable_area_opt_during_postlayout_opt = TRUE
compile_ok_to_buffer_during_inplace_opt = FALSE
reoptimize_design_changed_list_file_name =
reports_be/ipo_swapped_cells.txt
reoptimize_design -in_place -only_design_rule
What am I doing wrong here?
- Jean-Marc Allard
HOL
( ESNUG 285 Item 9 ) ----------------------------------------------- [4/3/98]
From: "Yan, Junjing" <junjing_yan@ccm.sc.intel.com>
Subject: Anyone Aware Of A Verilog->SPICE Converter?
Hi, John,
Does any one know any netlist convertion program or script that converts
a Verilog netlist to a HSPICE netlist?
- Junjing Yan
Intel
( ESNUG 285 Item 10 ) ---------------------------------------------- [4/3/98]
From: Don_Monroe@ne.3com.com (Don Monroe)
Subject: So.... What's The Real Story On The New Synopsys DW PCI Core ?
John,
I had some experience with Synopsys PCI core about 2 1/2 years ago and
remember a few articles in esnug about it as well. If I remember correctly,
Synopsys pulled it from the market. Now I understand that it is back on
the market. Does anyone have any experience with the current core
specifically at 64 bits and 66 MHz? How about the Virtual Chips core?
- Don Monroe
3Com
( ESNUG 285 Item 11 ) ---------------------------------------------- [4/3/98]
From: Testa Gualtiero <gualtiero.testa@italtel.it>
Subject: Are The EDA Vendors Planning On Abandoning HP-UX?
Hello John,
I've received several feedbacks from our ASIC and FPGA vendors regarding
their plans to abandon the Hp-UX platform or, in other words, to support
only Sun Solaris for their next software releases. Some examples: LSI
Logic FlexStream 1.0, SGS Thomson UDK 2.0 and Actel Designer Series R2-1998.
I don't know if these are false feedbacks due to some misunderstandings
between their European and USA departments. Have you heard something on
this issue?
- Gualtiero Testa
ITALTEL S.p.A. Milano, ITALY
|
|
