From: <michael.santarini=usr domain=reedbusiness hot mom>
Hey John,
Did you see that I got a scoop on EE Times with the Xilinx-AccelChip
story? http://www.edn.com/article/CA6298824.html Times didn't catch
on until 2 days later! Xilinx didn't announce it until 2 days after
I broke it, too. Xilinx was stunned I had found out their story
before they announced it. I've had good luck with these. I think
this is my 14th M&A scoop.
- Michael Santarini
EDN Magazine San Jose, CA
( ESNUG 450 Subjects ) ------------------------------------------- [01/25/06]
Item 1: ReShape's Farewell Letter; Tera Systems Weirdly Silent these Days
Item 2: Fishtail False Paths Benchmark Well; Multicycle Paths Not So Well
Item 3: User resents Secret Ambush Changes in how DC Fundamentally Works
Item 4: ( ESNUG 448 #1 ) Magma follow up on the Power Demo user questions
Item 5: Mentor FormalPro user very Concerned about it being End-of-Lifed
Item 6: How to force PrimeTime to produce a Multiple-Input Change Vector?
Item 7: An Easier Way I can report Global Net Worst Delays in PrimeTime?
Item 8: User asks how do you add Intelligent Margins in your Design Flow?
Item 9: Some colorful Q&A follow-up concerning the recent Synopsys Census
Item 10: ( ESNUG 443 #1 ) Two customers detailed reviews of Mentor Vstation
Item 11: ( DVcon 05 #15 ) Four users gush about Cadence Palladium emulation
Item 12: User seeks David Black's olde "logscan" Utility back from SNUG '98
( ESNUG 450 Jobs Section ) --------------------------------------- [01/25/06]
Job 1: Los Gatos, CA -- IC Manage seeks 2 EDA development engineers
============================================================================
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/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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