"I don't know what kind of HDL most ASIC designers will use in the
year 2010, but it will be called 'Verilog'."
- Steve Golson at SNUG 2002
( ESNUG 466 Subjects ) ------------------------------------------ [07/12/07]
1.0 Intro to Stu & Don's 58 Verilog and System Verilog gotchas
2.0 Declaration gotchas
2.1 Case sensitivity
2.2 Implicit net declarations
2.3 Escaped identifiers in hierarchy paths
2.4 Verification of dynamic data
2.5 Variables declared in unnamed blocks
2.6 Hierarchical references to declarations imported from packages
2.7 Variables with no hierarchy path are not dumped to VCD files
2.8 Shared variables in modules
2.9 Shared variables in interfaces, packages, and $unit
2.10 Shared variables in tasks and functions
2.11 Importing enumerated types from packages
2.12 Importing from multiple packages
3.0 Two-state gotchas
3.1 Resetting 2-state models
3.2 Locked state machines
3.3 Hidden design problems
3.4 Out-of-bounds indication lost
4.0 Literal number gotchas
4.1 Signed versus unsigned literal integers
4.2 Default base of literal integers
4.3 Size mismatch in literal integers
4.4 Literal number size mismatch in assignments
4.5 Literal number Z and X extension backward compatibility
4.6 Filling vectors
4.7 Passing real (floating point) numbers through ports
4.8 Port connection rules
4.9 Back-driven input ports
5.0 Operator gotchas
5.1 Self-determined operations versus context-determined operations
5.2 Operation size and sign extension in assignment statements
5.3 Signed arithmetic
5.4 Bit select and part select operations
5.5 Increment, decrement and assignment operations
5.6 Pre-increment versus post-increment operations
5.7 Modifying the same variable multiple times in an assignment
5.8 Operator evaluation short circuiting
6.0 Programming gotchas
6.1 Assignments in expressions
6.2 Procedural block activation
6.3 Combinational logic sensitivity lists
6.4 Arrays in sensitivity lists
6.5 Vectors in sequential logic sensitivity lists
6.6 Operations in sensitivity lists
6.7 Sequential blocks with begin...end groups
6.8 Sequential blocks with partial resets
6.9 Blocking assignments in sequential procedural blocks
6.10 Evaluation of true/false on 4-state values
6.11 Mixing up the not operator ( ! ) and invert operator ( ~ )
6.12 Nested if...else blocks
6.13 Casez/casex masks in case expressions
6.14 Incomplete or redundant decisions
6.15 Out-of-bounds assignments to enumerated types
6.16 Statements that hide design problems
6.17 Simulation versus synthesis mismatches
7.0 Testbench gotchas
7.1 Multiple levels of the same virtual method
7.2 Event trigger race conditions
7.3 Using semaphores for synchronization
7.4 Using mailboxes for synchronization
7.5 Coverage reporting
7.6 $unit declarations
7.7 Compiling $unit
8.0 References
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\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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