"If you can take advantage of a situation in some way, it's your
duty as an American to do it. Why should the race always be
to the swift or the jumble to the quick-witted? Should they
be allowed to win merely because of the gifts God gave them?
Well, I say cheating is the gift man gives himself."
- C. Montgomery Burns, quoted in honor of Item 1 below
( ESNUG 467 Subjects ) ------------------------------------------ [07/26/07]
Item 1: Cadence warns that a rival is cheating on 65 nm router benchmarks
Item 2: Carl's top 20 best selling Springer books at DAC'07 in San Diego
Item 3: ( ESNUG 461 #3 ) We moved to BlastCreate/Conformal due to a DC bug
Item 4: ( ESNUG 465 #3 ) Why is the DC-to-Formality guidance a "secret"?
Item 5: ( ESNUG 466 #2 ) Follow-ups to Stu & Don's 58 SV gotchas paper
Item 6: ClearShape in TSMC Ref 8.0 is an empty marketing trick, not real
Item 7: Anyone know what happened to Arcadia Design & their Mustang tool?
Item 8: The EDA industry itself chose to fire EE Times' Richard Goering
Item 9: The 14 gotchas we found while using the new PrimeTime DMSA tool
Item 10: User asks about Magma mystery "Viper" project -- Is it Mojave II?
Item 11: Mike Dini eviscerates Synplicity for its recent Hardi acquisition
Item 12: Anyone compare Atrenta Spyglass CDC vs. Cadence Conformal CDC?
Item 13: Why do PrimeTime-SI and VCS have 2 very different timing models?
Item 14: Magma, Virtuoso, Mike Stabenfeldt, SiCanvas, Tanner, and Synopsys
Item 15: ( ESNUG 465 #7 ) Cliff goes all postal on "default_nettype none"
Item 16: EDA research that Aart & Wally & Rajeev don't want you to know
( ESNUG 467 Jobs Section ) -------------------------------------- [07/26/07]
Job 1: Santa Clara, CA - Atoptech is looking for apps engineers
Job 2: FishTail seeks AEs based in San Jose, San Diego, Irvine
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 24,298 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
|
|
