The Wiretap Intercept No. 060627
opinions and skeptical speculations too small to fit into an Industry Gadfly column

> ... Therefore in my book, any savings claims above 14.5 percent are the
> results of cooked benchmarks where they cherry picked non-random routing
> points to make the X Architecture look better than it is; or its the
> relative measure of the inefficiencies of the various routing software
> tool(s) used.  In other words, their 20% wire reduction claim is notably
> inflated, but it's at least somewhere in the expected 14.5% ballpark.
> It's what EDA marketing people do.
>
>     - from http://www.deepchip.com/wiretap/060531.html


From: Hank Walker <walker=user domain=cs.tamu.edu>

Hi, John,

Regarding your Wiretap 060531, it is impossible to gain 20% benefit in total
wire length.  Apart from your discussion about 29% being the best case, a lot
of the wiring is on M1 and M2 within cells, and that isn't involved at all.

Also, many global signals such as clock and power are structured (e.g. mesh)
and need fewer diagonal routes.  So in total wire length, there can't be that
much benefit.

What Cadence might really be claiming is that there is a 20% benefit on the
"long signal routes", which of course is what the X Initiative is really
targeting.  And using your analysis, it is very unlikely the benefit can be
20%.  Even 14.5% seems very suspicious since placement will tend to minimize
the randomness of the routes.  Also consider that most routes will have the
X or Y distance significantly longer, so the diagonal jog is proportionally
a smaller fraction of the total distance.  Also consider that the length
reduction has to be enough to justify using diagonal layer resources.

I'd say that a more honest statement might be that there is a 10% benefit on
signal routes where interconnect length matters.

    - Duncan (Hank) Walker
      Texas A&M University                       College Station, TX


  Editor's Note: In EDA academic circles Hank is well known for his work
  in defect-based testing, IDDQ, and fault modeling.  I've always liked
  receiving his emails because he's one of the few EE profs I've known
  who was grounded in real day-to-day design issues.  Go Aggies!  - John
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