From: jmott@atmsys.com (James Mott)
> Hi John, In light of Cadence's recent suit against Cooper & Chyan
> Technology (CCT), I now believe that Cadence is following the usual
> pattern of technologically lagging/backward companies, and suing to
> hamstring competitors who have superior products under the guise of
> protecting their "intellectual property".
>
> Cadence originally developed a place and route package better than
> Silvar-Lisco, but it has bought all of its other innovations such as
> Dracula DRC, LVS, & Verilog. The fact that it is getting into consulting
> shows me it is a company with no real product plans, no product
> improvement goals, and is no longer innovative. Cadence must be stagnant.
> In the past, it would have just bought Avant! or CCT.
>
> I don't believe the injunction, halting sales of Avanti products, should
> be granted. Your reader who said: "WOULD NOT -- once granted, the
> company's dead. There's no appeal after death." was exactly right.
>
> Feel free to print this in ESNUG, John.
>
> - Jim Mott
> Atmsys
Editor's Note: Jim's letter is typical of what I've been getting since
the Cadence / CCT lawsuit news broke. It seems that engineers don't
approve of this latest legal maneuver by Cadence; not a single one has
taken a pro-Cadence stance.
- John Cooley
the ESNUG guy
( ESNUG 247 Item 1 ) -------------------------------------------- [8/96]
From: carl@compass-da.com (Carl Newhouse)
Subject: Comparing Two Synopsys/Compass Floorplanning Design Flows
John, in using COMPASS ChipPlanner with Synopsys synthesis for floorplanning
there are two basic approaches:
1) Traditional SDF Low level timing constraints - Timing constraints
that can be passed from Synopsys to ChipPlanner or vice versa via SDF
or a Synopsys constraints file. These Synopsys constraints are
typically in the form of a single constraint per path, or paths which
get constrained via -max_paths -nworst, -cover_design options. The
cover_design in Synopsys generates a constraint for the worst path
through every single input pin of each cell in the design. This
provides essentially complete coverage of the design. There are 2
flows using traditional low level constraints:
a.) Forward Annotation Flow (Synopsys-> ChipPlanner) -- Feed SDF or
Synopsys constraints into the floorplanner to perform timing
driven placement.
b.) Back-Annotation Flow (ChipPlanner->Synopsys) -- Feed SDF and
Synopsys Parasitic Command FIle (containing set_load,
set_resistance, etc.) information for IPO (Inplace Optimization).
PDEF is also generated so Floorplan Manager can take into account
the physical hierarchy during IPO. COMPASS can also generate
selective timing path (SDF out).
2) High level Timing Constraints -- These are constraints independent of
the exact timing path. The constraints apply to a block or the entire
design. Typical high level constraints are: frequency, external delays,
path clusters, multi-cycle constraints etc. The Compass ChipPlanner
Floorplanner (MakeTime Option) can take these Synopsys constraints and
perform placement of the standard cells and eliminate the need to
generate SDF to feed back to the synthesis enviroment. Some specific
examples of Synopsys constraints that can be read into ChipPlanner:
create_clock -name clk -period 20
set_input_delay 3 -clock clk input1
set_output_delay 3 -clock clk output1
report_timing
This approach avoids useless speeding up non-critical paths and lets
the designer use the same Synopsys constraints for synthesis and
floorplaning.
In a nutshell, the two basic flows are:
Using Low Level Constraints Using High Level Constraints
===================== ======================
1 Synthesize Synopsys Synthesize Synopsys
2 Floorplan 1 Floorplan with High level constraints
3 Generate SDF 2 Analyze Timing in Floorplan
4 Load SDF 3 Perform IPO in Floorplan
5 Analyze Timing in Synopsys <Repeat Steps 1-3 if necessary>
6 Synopsys In-Place Optimization
7 Floorplan with ECO changes
<Repeat Steps 3-7 if necessary>
Benchmarking the two basic flows, using a 300K gate cell-based design, I
found the high level approach only took 10 minutes to read into ChipPlanner
(because it was digesting only a 1K constraints file) and 3-4 iterations
were typical. I don't know details for the traditional flow but I suspect
it'll be longer because the traditional SDF low level constraints took ~5
hours just to read into Synopsys (because it's reading a 60MB SDF file.)
I don't have any numbers on how long the entire steps 3-7 would take. It
would be nice to know.
- Carl Newhouse
Compass Design Automation
( ESNUG 247 Item 2 ) -------------------------------------------- [8/96]
Subject: (ESNUG 243 #2 246 #2) Synopsys 3.4b Won't Use 8->1 Multiplexers
> Synopsys can not automatically map anything with more than 8 inputs into a
> logic funtion. Therefore an 8:1 mux (which has 8+3=11 inputs) will never
> get chosen! You must actually instantiate it like ...
From: Ross Swanson <swanson@est07.bwi.wec.com>
John, For a 8:1 mux I coded a "case" statement with an integer for the
expression and got a 16:1 built, the 2:1 and the other 8:1 were optimised
out! I'm using v3.4b with the infer_mux attribute.
- Ross Swanson
Northrop-Grumman
---- ---- ---- ---- ---- ---- ----
From: krag@lsil.com (Kevin R. Grotjohn)
John, Regarding the infer_mux directive in 3.4a, I tested this new feature
using LSI lcbg10p library using the examples in the Synopsys application
note (DOC-111195). Design Compiler inferred our lcbg10p/mux81h cell just
fine. There are a lot of compiler directives and RTL conventions that
impact how well this works though. In older versions you do have to
directly instantiate it.
Synopsys 3.4a can map to large input function cells, I have tested it for
all logic functions of up to 12 inputs. I assume it can do even higher
input functions -- but congestion problems do become an issue which DC
does not consider.
- Kevin R. Grotjohn
LSI Logic
---- ---- ---- ---- ---- ---- ----
> Unfortunately there is no easy way to instantiate multiple components in
> Verilog (in VHDL you can use "generate", but even this is crude.)
> I have built a user designware module called "mux_gen" where you can just
> pass parameters and get one built like you want. (Note: Kurt Baty has
> created a module he calls "mux_any", while mine is similar in function...
From: kurt@wsfdb.com (Kurt Baty)
Hi, John,
The DW01_mux_any is on the Synopsys 3.4b DesignWare CDROM. If you are
running 3.4b and you want to know if the mux_any part is available for you
to use, type the following Unix command:
% ls $SYNOPSYS/dw01/lib/DW01_MUX_ANY*
/cadapps/synopsys/synopsys_3.4b/dw01/lib/DW01_MUX_ANY.mra
/cadapps/synopsys/synopsys_3.4b/dw01/lib/DW01_MUX_ANY.sim
/cadapps/synopsys/synopsys_3.4b/dw01/lib/DW01_MUX_ANY.syn
/cadapps/synopsys/synopsys_3.4b/dw01/lib/DW01_MUX_ANY_CFG_SIM.sim
/cadapps/synopsys/synopsys_3.4b/dw01/lib/DW01_MUX_ANY_CFG_STR.sim
/cadapps/synopsys/synopsys_3.4b/dw01/lib/DW01_MUX_ANY__SIM.sim
/cadapps/synopsys/synopsys_3.4b/dw01/lib/DW01_MUX_ANY__SIM.syn
/cadapps/synopsys/synopsys_3.4b/dw01/lib/DW01_MUX_ANY__STR.sim
/cadapps/synopsys/synopsys_3.4b/dw01/lib/DW01_MUX_ANY__STR.syn
If you see these files, then the mux_any is available for you to use. It
maps 8:1 muxes. The documentation will, of course, be in the next release.
The part really wasn't supposed to be on the 3.4b CDROM. It was supposed to
be on the 3.5a.
You can use the part as the following Verilog code example shows:
module mux(data_in,mux_sel,data_out);
parameter out_width = 8, sel_width = 5, in_width = 24*8;
input [in_width-1:0] data_in;
input [sel_width-1:0] mux_sel;
output [out_width-1:0] data_out;
wire [out_width-1:0] data_out;
DW01_mux_any #(in_width,sel_width,out_width) mux(data_in,mux_sel,data_out);
endmodule
The only times 8:1 muxes may not be chosen are 1) if your library's 8:1 mux
has an enable pin or 2) the 8:1 speed is less than stacked 2:1 or 4:1s and
you have a high map effort compile.
- Kurt Baty
WSFDB Consulting
( ESNUG 247 Item 3 ) -------------------------------------------- [8/96]
Subject: ( ESNUG 246 #8 ) Benchmark & User Opinions On Hardware Emulators
> I am currently engaged in benchmarking several emulation verification
> technologies in the market place such as Synopsys' Arkos Emulator, Mentor's
> Meta emulator, Aptix, Virtual Machine Works and fill-me-in on vendor
> against Quickturn's Emulation Systems. ... I would like to hear comments on
> ESNUG from people who are thinking/considering/benchmarking/using any of
> the above emulation systems.
// Synopsys ESNUG anonymous contribution mode ON
From: [ Call Me Ishmael ]
John, Here are my impressions of the hardware emulation market.
Quickturn -- In business for 4 years and I've used it a lot. Their
first generation was very bad in terms of usablity & friendliness; but
lately has gotten better. Their product works now. Their hardware
got more reliable and 2X to 4X faster. Their so-so software hasn't
changed. They claim better software is coming soon. Designs in the
~500 kgate range take a full day + night to compile. ("Compiling"
means your netlist is partitioned into "logic modules" that hold
about 250k gates each, followed by doing the Xilinx P&R on the 80 FPGAs
in each "logic module".) They can handle multiple clocks, but no Verilog
or VHDL co-simulation -- only gate-level stuff. Their tweek cycle (the
time to modify & recompile a few gates in a netlist) is about an hour.
I really like their built-in analyzer and 100% visibilty. You can
look at any node in a design as you step through cycle by cycle. Costs
U.S. $1 to $1.3 per gate emulation. They also give great DAC parties.
Synopsys Arkos -- My initial impression is that their speed won't match
Quickturn's, but they will do much better with ease-of-use and features.
They offer RTL Verilog & VHDL co-simulation. Non-synthable behavioral
RTL runs on your workstation interacting with the Arkos box. It can
handle multiple clocks and claims to integrate well w/ Synopsys's other
EDA tools. Has automatic partitioning into 200 kgate non-FPGA boards
with supposedly fast compile times. Don't know costs per gate. Still
lots of other unknowns, lack of documentation, etc. They claim ~$10
million in sales, but give no names. They have variable DAC parties.
Aptix -- Price leader. U.S. $0.50 (or less) per gate emulation. But
size limit of ~100 kgates and it's the Radio Shack kit of emulators.
You get a board, not a box, and you spend a lot time shuffling FPGAs
in and out of it. You provide your own Tektronix/HP logic analyzer
for debugging. Fast compiles and simulation times. No DAC parties.
Mentor's Meta-Systems -- Still vaporware. For example they said it can
handle multi-clocks, but when we looked into it they later said: "Woops!
That's in the next release!" They claim to be working on a Verilog/VHDL
co-simulation but it's not here today. Quickturn lawsuit causes some
concern because it supposedly limits their sales to France, England,
and Israel -- but Mentor claims they can sell what boxes they have
already imported. They also claim they're about 50 percent cheaper than
Quickturn. It all seems very shakey. They also have great DAC parties.
Virtual Machine Works -- never heard of them.
Overall, hardware emulation is usually 6X faster than software simulation, so
I'm very willing to trade a little speed for better features and usability.
- [ Call Me Ishmael ]
// Synopsys ESNUG anonymous contribution mode OFF
( ESNUG 247 Item 4 ) -------------------------------------------- [8/96]
Subject: (ESNUG 245 #1 246 #4) My Multicycle Path Odyssey With Synopsys...
From: jaf@arl.wustl.edu (Andy Fingerhut)
> process (CLK)
> begin
> if (CLK'event and CLK = '1') then
> if (change_B = '1') then
> B <= A + 1;
> end if;
> end if;
> end process;
From: mr@symbionics.co.uk (Martin Ryder)
>It should be possible to build a 2-to-1 MUX from logic primitives (AND, OR,
>NOT) to give correct behaviour when the two data inputs are the same,
>regardless of whether the select is known. I.E. for data inputs A and B,
>select S, and output Q .......
From: kurt@wsfdb.com (Kurt Baty)
Hi, John,
As Martin suggests, Andy's muxes can be structured as logic primitives to
get around the select "x" problem. The circuit that correctly creates an
enable-able register row has a side benefit that it can be reset to any
value at no extra logic cost per bit. This circuit design is in DesignWare
DW03_reg_s_pl, a register with synchronous set and/or reset and load.
The design employs only two cells per bit. An AOI2N2 or an OAI2N2 and a
D flip-flop are employed per bit, depending on the reset value desired,
a one or a zero. These gates are in most technology libraries, so the
GTECH part should map exactly. This circuit generates a safe
synchronously loadable, synchronously resetable register. It is
guaranteed to come out of reset cleanly, however, do not ungroup
it and do any kind of compile or the retained AND could be optimized away.
If you wish to ungroup it, just don't do a compile afterwards.
This part has been in the library for some number of revs. It's in the
online documentation as well as the DesignWare data book. If you wish to
see the circuit it generates, set the target library to "gtech.db" and
elaborate and compile one.
- Kurt Baty
WSFDB Consulting
( ESNUG 247 Item 5 ) -------------------------------------------- [8/96]
Subject: (ESNUG 244 #6) Synopsys Online Documentation & WorldView 2.1
> Recently we've installed Synopsys 3.4b and when trying the online
> documentation I noticed some odd behavior. ... Upon startup, the
> "Search->Collection" window pops up automatically after the welcome page
> is displayed. How can I suppress this behavior? ... Does anyone have some
> tips on how to use the printerConfig Xresource with WorldView 2.1? I
> would like to be able to print, for example, two pages on one (using pl2ps
> and PSUtils) directly from WorldView. Using only a filter didn't work,
> but using pl2ps and the PSUtils on UNIX level did.
From: kamphuis@earl.hl.siemens.de (Peter Kamphuis)
John,
I found out how to print two pages on one directly from WorldView.
Following is described for Synopsys 3.4b with WorldView 2.1.
First you need access to PSUtils. PSUtils is a set of public domain
PostScript converting tools by Angus J.C. Duggan. We have them installed in
/usr/local/bin, but you should find them in the Internet (try some ftp
server with a path like .../applications/textproc/Postscript/psutils).
Then you need to create a script that creates PostScript from the WorldView
*.pl files, converts it and sends it to your printer. You'll find two
scripts (iviewspool, iviewspoolb) below. They must be available to
WorldView through your PATH variable.
Finally you need to setup the printerConfig resource in your Iview file
as follows:
Iview*printerConfig: myprt_dbl, PostScript; \
myprt_dbl (2 on 1), External, iviewspool %s %s; \
myprt_dblse (booklet), External, iviewspoolb %s %s;
Note that many of our printers are network HP Laserjets with a duplex unit.
The name "myprt_dbl" sets up the printer for double sided printing with long
edge binding, the name "myprt_dblse" does the same, but with short edge
binding, needed for booklets. Especially converting to booklets is nice for
printing out the quick references. If you don't have a duplex printer, you
could use psselect from PSUtils to select only odd or even pages and print
out twice.
Below you'll find the two scripts that show a simplified version of my
(only one) script. My original script contains some more checking, etc.
that would be too long for posting here. You can contact me for more
information.
Note that I've used European paper formats, use the appropriate US formats
("Letter") as necessary. I also had font problems when printing out the
normal online documentation. You must use the print collection: follow the
"Demand Printing" link.
#!/bin/csh -f
# iviewspool: Alternate printer spooler for iview. Generate 2 pages on 1.
set PRT = ${1}
set BOOKFILE = ${2}
set PL2PS = "${SYNOPSYS}/worldview/bin/pl2ps"
set PSNUP = "/usr/local/bin/psnup"
${PL2PS} -D -dps A4 -e -ft 3 -hdr False -i ${BOOKFILE} -rm 0
| ${PSNUP} -2 | lpr -P${PRT}
# EOF #
#!/bin/csh -f
# iviewspoolb: Alternate printer spooler for iview. Generate booklet.
set PRT = ${1}
set BOOKFILE = ${2}
set PL2PS = "${SYNOPSYS}/worldview/bin/pl2ps"
set PSRESIZE = "/usr/local/bin/psresize"
set PSBOOK = "/usr/local/bin/psbook"
set PSNUP = "/usr/local/bin/psnup"
${PL2PS} -D -dps A4 -e -ft 3 -hdr False -i ${BOOKFILE} -rm 0
| ${PSRESIZE} -pA3 | ${PSBOOK} | ${PSNUP} -2 -b30 | lpr -P${PRT}
# EOF #
I hope this is useful. Ideas and comments are welcome.
- Peter Kamphuis
Siemens Semiconductor, Munich
( ESNUG 247 Item 6 ) -------------------------------------------- [8/96]
Subject: ( ESNUG 246 #6 ) Is DesignWare Worthwhile Or A Waste For Fast DSP?
> I have a team starting a LSI Logic 0.35 micron CMOS, cell based design.
> Chip is fancy two stage FIR filter. First stage is 240 MHz input
> decimator, no multiplies, precomputed lookup and add. ... We have been
> debating the usefulness of DesignWare. Some contend it will
> save time to instantiate pre-optimized Designware functions. Some say we
> are wasting our time because the speed is so high the Designware functions
> are going to require additional optimization and get overhauled like
> everything else. Any recommendations?
From: khelifi@cae.ca (Djoudi Khelifi)
John, DesignWare is useful in this case if:
1- your functions are reused in many designs with the same bit width
2- and/or your functions are so complex (functionality or big width)
3- your functions are pipelined parts
In these cases, the time to (bc_time and schedule your design) will be
reduced and you will get an accurate estimate for area and timing. On
the other hand, the optimization of your precompiled functions requires a
run time which is proportional to your area and timing constraints.
- Djoudi Khelifi
CAE ELECTRONICS Ltd, Canada
---- ---- ---- ---- ---- ---- ----
From: ryan@fsd.com (Ken Ryan)
Hi, John, my 2 cents...
I evaluated DesignWare for a fast arithmetic pipeline. It turns out that
while design entry would have been easier using DW parts, my own structures
were faster and smaller (some several times, when I could roll multiple
operations into, say, a single Wallace tree). I daresay you could put in
pipeline registers and get as fast as you need, at the cost of more gates.
What also scared me away was that DesignWare is fairly expensive and is
licensed yearly, which was not a cost-effective solution for me.
- Ken Ryan
Orbital Sciences Corp.
---- ---- ---- ---- ---- ---- ----
From: Steve Hwang <steveh@8x8.com>
Hi, John
Recently, I just did some benchmarks on Synopsys Designware. We have
a number of multipliers (17 bits, 33 bits), and the performance of Synopsys
Designware is equal or better than our custom multipliers. We are using
UMC 0.35um standard cell library (in house developed), with the "SS" library
operating condition (TT device model, 125C, 2.7V). With 17 bits "wallace"
type multiplier, we could achieve 10.54ns (Synopsys) for the worst path
delay while our full custom block has a worst path of 11ns (Epic pathmill).
The only catch is the layout area. Full custom is much smaller than the
standard cell layout, but we think if we are using other commercial
datapath layout tool we can further optimize the area and timing of
Synopsys DesignWare.
In our design, it is pad limited design, so the area is not as critical
as other issues (tapeout date).
- Steve Hwang
8x8, Inc.
---- ---- ---- ---- ---- ---- ----
From: krag@lsil.com (Kevin R. Grotjohn)
John,
The advantage of DesignWare is that it is generic and can be mapped to
multiple vendors choosing the best architecture and cells based on
area/speed constraints. However if you are doing pipelined DSP you
will need to instantiate the DesignWare parts (DW02_sum, DW02_mac),
since they will not be inferred from the RTL. If you have the LSI TOOLKIT,
invoke lsilbs and choose SuperMacGen; which is an ideal generator for
DSP because it use custom cells in an delay optimized/pipelined sum of
products architecture. Compile time is an order of magnitude faster
than DesignWare, since the technology mapping step does not need to be
done.
I think the unpipelined 16 bit multiply is done in 8ns (lcbg10p), and
you can do even better if you build a pipelined sum of products for
your application. Our multipliers are always faster than Designware,
and we also have a faster parallel adder if you hand place the cells.
- Kevin R. Grotjohn
LSI Logic
( ESNUG 247 Item 7 ) -------------------------------------------- [8/96]
From: "Tom Tomazin" <tomt@it.sps.mot.com>
Subject: Trying To Find An Equivalent Function Found In Design_Analyzer
Hi, John,
In design_analyzer, under the Analysis menu, there is an option to "Show
Net Load...". When you select a net, it gives the capacitive load on that
net as applied by the wire load model and the std cell pins connected to
that net. I need a analogous command in dc_shell to extract this info.
Anyone know the ultra secret command that will do the same in dc_shell?
- Tom Tomazin
Motorola
( ESNUG 247 Item 8 ) -------------------------------------------- [8/96]
From: doering@sylt.iti.mu-luebeck.de (Andreas Doering)
Subject: EDIF Properties & Bypassing FPGA Compiler Name-Changing Problems
Hello John,
I use Synopsys FPGA compiler and Altera Maxplus2 for designing (currently)
CPLDs of the MAX9000 family. I have a design where I need to do some clique
assignments to convince mp2 that a certain module really fits into one LAB.
I have tried this editing the .acf file manually but this is really ugly,
since the device names FPGA Compiler produces permanently change.
Furthermore I like having it all together in one file.
In the EDIF netlist reader documentation is described how an EDIF property
field has to look like to be interpreted as resource assignment by mp2.
Now the question is, how do I force Synopsys to write these property
constructs? There is an EDIF variable called edifout_write_properties_list.
The man-pages say, that the corresponding properties will be written out in
EDIF. How do I set these properties? Can I set a property like "clique"
to "my_clique"? I first assumed that user defined attributes and properties
are the same, but the VHDL Compiler does not let me define attributes for a
design for synthesis!
- Andreas Doering
Medizinische Universitaet zu Luebeck
( ESNUG 247 Networking Section ) -------------------------------- [8/96]
Sunnyvale, CA -- Ventritex seeks several custom I.C. designers with Verilog
experience to design medical equip. No headhunters! "kcarroll@ririus.com"
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