I have a group of friends who rent a cottage on Cape Cod every Mother's
Day and throw a weekend party for about 110 guests. This recent Mother's
Day was no different. On the Saturday of the weekend, nine of the young
& single crowd decided to go horseback riding. Five women and four guys.
Cool. When we got to the stables, we noticed lots of women and girls
around but we four men were the only human males present. We men joked
privately to ourselves that we had hit "Babe-Mecca: the Mythical Activity
That Involved Lots of Happy, Single Women And Very Few Men!" Yea!
We all got our horses, saddled up, and the guide (also a woman) took
us on the trails. Everyone was having a fun time. Yea! We guys were
telling jokes and the girls were happily yaking up a storm about this,
that, and the other thing. Fun! Suddenly the guide decided to have all
the horses trot. And just as suddenly all of the men became very quiet
while the women kept laughing and even joking, too. It became extremely
clear why men don't ride horses and why God invented stirrups. Because I
suddenly found myself standing in those very same stirrups to avoid the
Sadism involved when a 750 lbs horse repeatedly slamming its body against
your groin. "Oh, God, please make the bad horsey walk, PLEASE!" :^(
- John Cooley
the ESNUG guy
( ESNUG 289 Item 1 ) ----------------------------------------------- [5/98]
[ Editor's Note: For the past few months I've been mercilessly badgering
Synopsys to publically tell me exactly who has been actually using
Behavioral Compiler for real, live chip designs. And, for the longest
time, I got the usual smoke & mirrors until recently... - John ]
From: Rajiv Maheshwary <rajiv@Synopsys.COM>
Subject: Naming Names About Who's Using Behavioral Compiler, Tapeouts, Etc.
Hi John,
Just completed a quick poll of our BC users and have some great news to
share... BC has crossed the 50 tapeout mark. Attached (below) are details
for 36+ HLS and 14 BOA/BRT. Current run rate is 1-2 tapeouts/month.
Now, I know we still have a number of open product issues (such as reduce
the need for DesignWare, etc..) but it is time for a celebration.
Happy BC'ing
- Rajiv Maheshwary
Synopsys BC Marketing
Details On 36+ HLS Tapeouts
---------------------------
Customer End Product Design Characteristics
---------------------------------------------------------------------------
Adtran Filtering ADSL Modem (2 chips of) 250k gates @ 50 Mhz
200k gates @ 50 Mhz
AMD 100 Mbps Fast Ethernet
Apple 600 dpi Inkjet Color Printer 20-30k gates @ 30 Mhz
20k gates @ 30 Mhz
Apple Set-Top Box Multimedia Mixer 100k gates @ 54 Mhz
60k gates @ 54 Mhz
Ericsson ATM Switch
Hughes Satellite DSP
Hyundai DVB Cable Modem Adaptive Equalizer 100k gates @ 50 Mhz
70k gates @ 50 Mhz
IKOS Hardware XL (2 chips of) 40-70k gates @ 66Mhz
Dataflow machine w/control 10-15k gates @ 66 Mhz
Intel Fixed Point Arithmetic Processor 41k gates @ 66 Mhz
Lucent Multi-level Scheduler Packet Router 50k gates @ 66 Mhz
50k gates @ 66 Mhz
Mitsubishi Audio Codec Phone 80k gates (2 chips)
Motorola 2 Way Paging
National 256k QAM Cable Modem 250k gates @ 125 Mhz
150k gates @ 125 Mhz
NEC CDMA Receiver (2 chips)
Nortel ATM Switch 170k gates @ 52 Mhz
Traffic Management Functions 50k gates @ 52 Mhz
Sanyo Digital Still Camera 81k gates @ 30 Mhz
28.6k gates @ 30 Mhz
Sharp Video Capture PC Camera 85k gates @ 48 Mhz
45k gates @ 48 Mhz
Siemens Roke Manor ATM Switch (2 chips of) 272k gates @ 66 Mhz
170k gates @ 66 Mhz
Symbol Wireless LAN 70k gates @ 20 Mhz
35k gates @ 20 Mhz
TI Cordless Phone ( 2 chips)
Details On 14 BOA/BRT Tapeouts
------------------------------
Customer End Product Design Characteristics
---------------------------------------------------------------------------
S3 3D Graphics 100k gates @ 125 Mhz
Cirrus 3D Graphics 240k gates @ 125 Mhz
DEC 3D Graphics Workstation 2M gates @ >100 Mhz
HP GigaBit Fiber Channel Switch (Using BRT only)
Hughes Satellite DSP (2 chips)
Number 9 3D Graphics 650k gates @ >100 Mhz
Analog Devices ADSL Modem 315k gates @35 Mhz
SGS-Thomson 3D Graphics Multimedia XL 150k gates @ 100 Mhz
Other customers 5+ (guesstimate) BOA/BRT module(s) range from 30k-150k gates
( ESNUG 289 Item 2 ) ----------------------------------------------- [5/98]
Subject: Tips, Gotchas, Todo's, Don't Do's, For A Mixed NT / UNIX Environment
> I work in a design group at Eastman Kodak and we are making a first
> attempt at setting up a mixed NT and UNIX environment for a new project.
> We have been very UNIX centric in the past. If it is possible I would
> appreciate any information that you feel free to share about any tips,
> gotchas, problems, todo, don't do, etc.
>
> - James Goeke
> Eastman Kodak Company Rochester, NY
From: <plaberge@micronpc.com>
Hi John,
We use model technology ModelSim for VHDL/Verilog simulation with NT. NT
works well and has a good memory manager. Memory requirements are based on
simulation size. We run some boxes with as much as 500MB of memory for gate
level sim. Typical behavior simulation uses 150MB of memory (for a 300K
gate asic). We use VHDL/Verilog dynamic memory allocation in our models to
keep the memory size down.
I wish the control language was TCL, but that may come in a future release.
I think TCL is used for the Unix version of ModelSim.
We shell out to the HPUX unix world to compile our bus functional model
code. This is done using the system command through model technology and
rsh from the NT command shell. Dos make is used to determine if a bfl
compile is necessary.
Our design database is on an NT file server and raid controller/box. We use
Intergraph's Diskshare NFS server software to serve the NT file system to
the UNIX machines. Then we can run Synopsys directly on our NT design
database. We use make on the UNIX side to determine the code that needs to
be synthesized.
Our design database broken up into projects (we also have shared code in a
common directory). Each designer is responsible for his own sythesis. The
top level is stiched together after everyone is done.
Scripting is a bit of a nightmare.
You'll need to spend some time in your simulator, command shell, NT scripting
(perl is available for NT), and of course unix. It's all doable and works
well for us.
Hope this helps.
- Wayne Miller
Symbol Technologies, Inc.
( ESNUG 289 Item 3 ) ----------------------------------------------- [5/98]
Subject: ( ESNUG 288 #5 ) DC 98.02 Creates Bad Logic With Floating Inputs!
> Just a quick note on a problem that sometimes shows up when compiling with
> high effort "on". (At least I believe that it only happens w/ high effort
> being used.) Sometimes the 1998.02 synthesizer will create logic with the
> inputs of some cells not connected to anything. If you follow the good
> practice of always doing "check_design" after synthesis, then it will flag
> it. Synopsys has a patch for the problem that seems to work (at least it
> worked for one of my blocks), the patch is 1998.02-1, and my FAE was
> very responsive when I flagged this problem and I had a fix within an hour
> (thank you). The scary thing to me is that I always compile with
> verify_effort high, and it didn't catch the problem - I'll be double
> checking the man pages to see what this option is supposed to be verifying.
>
> - Victor J. Duvanenko
> Truevision
From: zalewski@cgc9.eda.mke.ab.com (George Zalewski)
John:
Supposedly there is a patch that fixes this bug, but I haven't applied
it yet. According to the readme file:
"This patch will only fix the problem in dc_shell. You will not be able
to use the workaround in Design Analyzer."
The instructions to get the patch were sent by a Synopsys representative,
and are included below. The documentation also mentions other cases during
which incorrect logic is generated.
Using the command-line FTP :
----------------------------
Substitute <arch> for your specific platform, either sparc, sparcOS5,
hpux10, or rs6000.
- Start an ftp session to "ftp.synopsys.com"
eg. % ftp ftp.synopsys.com
- Enter "anonymous" as the login name.
- Enter your <email address> as the password.
- Type "binary" at ftp prompt to set the transfer mode to binary:
ftp> binary
- Type the following command(s) to receive the files:
ftp> cd pub
ftp> cd syn_1998.02-1_<arch>
ftp> get syn_1998.02-1_<arch>.readme
ftp> get syn_1998.02-1_<arch>.tar.Z
ftp> get syn_1998.02-1_<arch>.pdf
ftp> get syn_1998.02-1_<arch>.ps
- To logoff the ftp server, type "quit"
The directory contains a readme file, release notes in postscript and pdf,
and the compressed tarfile for the software. I am enclosing the
postscript version of the release notes in this email.
The tarfile contains the following executables:
dc_shell_exec
dp_shell_exec
dt_shell_exec
dc_view_exec
estm_shell_exec
lc_shell_exec
lcgui
ra_shell_exec
rtl_analyzer_exec
bc_view_exec
ptxr_exec
schedule
These executables will continue to use the 1998.02 root directory. Customers
should copy these files into the $SYNOPSYS/<arch>/syn/bin directory.
- George Zalewski
Allen-Bradley Milwaukee, WI
( ESNUG 289 Item 4 ) ----------------------------------------------- [5/98]
Subject: ( ESNUG 288 #10 ) Escalade vs. Summit and Mentor Renoir vs. Speed
> I was wondering if anyone else is looking at Escalade's Design Book
> as an alternative to Summit and Mentor's Renoir?
From: Geir Harris Hedemark <geirhe@hridil.ifi.uio.no>
I have tried the release of Renoir (on NT) Mentor distributed last fall. It
had quite a few bugs, and I was not impressed after having read the four
color glossies. The HPUX version was even less streamlined than the NT one.
I have not been able to test the latest (C.1) release yet, but I strongly
suspect things are better now.
Vicious tongues say that Renoir is a blueprint of Summit's graphical entry
tool. I have not tried Summit's tools myself, and cannot say whether this
is true.
But over to graphical entry: I quickly found that graphical entry was not
the thing for me. I spent way too much time moving graphical thingamabobs
around on the screen relative to the time I spent actually doing something.
I think a good VHDL programmer is able to write program code much faster
(and visualize it in his own head) than a graphical entry tool can show you,
provided he has got a good editor that helps him write VHDL.
However, I will be using Renoir the "other way around", for making
documentation. Once I have written and tested my VHDL code, I am going to
stuff the VHDL code into Renoir to make Pretty Pictures of it. This will
enable people that are not fluent in VHDL to double-check the functional
correctness of my code. I think that will be a great bonus, well worth any
licensing fees (within reason). It will also ensure (providing Mentor has
done their job) that the documentation corresponds to the implementation.
Stuffing VHDL code into Renoir isn't a time-consuming task, either, and I
won't wreck my lower hand tendons doing it.
Note that I am an emacs/unix diehard and a quite fast typist. I use lynx
when I surfe the web, and I don't like using a mouse more than absolutely
necessary. YMMV.
- Geir Harris Hedemark
University of Oslo, Norway
---- ---- ---- ---- ---- ---- ----
From: zuk@ll.mit.edu (W. S. Zuk)
We have used Speed Electronic's speedchart since 1995 with great success.
We used it for entire, top down chip design, not just "state machines".
Unfortunately, Speed Electronic went out of business last August.
Ironically, Mentor bought the assets of Speed and hired some of the staff.
IMO, the product Mentor should have copied is Speed. In fact, since they
now own the Speed source code, IMO they should just add a button to their
Renoir GUI to enable the Speed tool, or better yet, just re-sell the Speed
product the same way they re-sell interconnectix and Model Tech.
I agree wholeheartedly that these "MS Windows" look & feel user interfaces
are so weak and un-automated for graphical drawing so as to be certainly
frustrating and nearly useless. A good, professional level graphical
entry tool designed for someone running the tool many hours a day (along
the lines of old fashioned unix-based schematic tools such as Viewlogic's
viewdraw) makes a huge difference in productivity. That is what Speed
offered. (Actually, I consider speedchart a generation ahead of viewdraw
in terms of automated drawing functions). All the other HDL graphic
offerings that I know of are "me too's" w/ a weak and overly cumbersome
drawing package.
I think it's inevitable as HDL designs get handed around among different
designers and get larger and larger that a good graphical tool will help
productivity and maintenance.
IMO the "old" speedchart tool had it right & allowed top down design entry
graphically.
- Bill Zuk
MIT
P.S. -- Is there life after death? I see there's an article about Speedchart
in the May 1998 issue of Integrated System Design magazine, pg38-48.
---- ---- ---- ---- ---- ---- ----
From: Mike Treseler <tres@tc.fluke.com>
I have evaluated several and have so far found nothing more efficient than a
good text editor and synthesis tools. I used to believe that I needed a
schematic view of the top level, but changed my mind after trying to do it.
My experience was that getting the "wires" right on a graphical view tried my
patience more than getting a concise text version of the same thing. I was
also surprised by how many gates and flops could spew from a few lines of
code.
I found that the "view schematic" function of the synthesis tool gave me all
the information I really needed to know about what was going on with the
primitives. With a graphical top level, you get a minimum of one block
diagram sheet then one other page describing each block. With text-only the
minimum is one page of text. So now if I need a block diagram, I draw it
in my notebook.
To answer your question, my favorite graphical tool and the easiest to
evaluate is Renoir. You can downloaded from mentor's website and get a
temporary key by email with no hassle. But get out your wallet if you want
to buy it.
The best deal for the money is a pencil and paper.
The second best deal for the money is CompLib (e-mail riitta@hantro.com)
- Mike Treseler
Fluke Networks Division Everett, WA
---- ---- ---- ---- ---- ---- ----
From: Geir Harris Hedemark <geirhe@hridil.ifi.uio.no>
Let us be fair. I don't think Mentor targets professional asic designers
with Renoir. I think they are targeting people who make an fpga now and
then. These people won't use the tool enough to be able to learn an
efficient graphical entry user interface (the emacs interface holy war
springs to mind here), and for them, Windows look and feel is just what the
doctor ordered.
- Geir Harris Hedemark
University of Oslo, Norway
---- ---- ---- ---- ---- ---- ----
> But over to graphical entry: I quickly found that graphical entry was not
> the thing for me. I spent way too much time moving graphical thingumabobs
> around on the screen relative to the time I spent actually doing something.
From: T Wang <tsuhua@cisco.com>
I totally agree with the above comment. Especially, try to draw a finite
state machine with 15 states, 45 transitions and 75 conditions. I'll spend
95% of my time to make my fsm look pretty and 3% of time to worry about my
fsm design.
I have discussed this matter with many experienced CAD & hardware designers.
Our conclusion is that they are not that useful.
However, Text2Graphics is very very powerful. We found TWO BUGs by examing
the fsm bubble diagram (no simulation). I call this "visual verification".
Also, designers bring their fsm bubble diagram for the code reviews.
In my opinion, the best bubble diagram drawing tool is AT&T's "dot" or
related products. And, it is FREE. To learn how we found two bugs, please
consult the IVC'98 paper:
http://www.employees.org/~ciscofsm
http://www.research.att.com/tools/graphviz
BTW, the paper shows, thanks to dot, the 15 states, 45 transitions and 75
conditions bubble diagram.
- Tsu-Hua Wang
Cisco Systems
---- ---- ---- ---- ---- ---- ----
From: Adam Atherton <atherton@syr.lmco.com>
I have used VisualHDL from Summit extensively in an FPGA design process and
found the block diagram schematic entry to be really good. I have never
used any others so I don't have much to compare it against though. The block
diagrams are easier to understand, and trace signals in, and the code that
was produced was extremely close to how I would have written it using a text
editor. For small designs, a text editor may have been faster, but in terms
of large designs, I found it invaluable. Also, as another incidental bonus,
you should have heard my program engineer raving about the quality of the
diagrams compared to my usual atrocious handwriting.
- Adam Atherton
Lockheed Martin Syracuse, NY
---- ---- ---- ---- ---- ---- ----
From: vincent@dtcs09.kodak.com (John Vincent)
In considering graphical HDL entry tools, you may also wish to consider
Escalade's Design Book product. We have looked at it a bit and seems to
have some advantages over other competitors in some areas. It really
depends on your objectives for the tools. We decided we needed to formally
assess users needs to decide which tool is best suited to our needs.
One thing I liked about Escalade was their ModuleWare library of
parameterized functions. These are nice for datatpath design and not
restricted to LPM functions. I consider these to be especially valuable to
new HDL designers. It was actually in looking for this capability that
learned of Escalade.
We have looked at both tools a little a while back. Escalade seemed to
be easier to use and more intuitive. It had some convenience features
in the state machine editor which Summit did not. We also had a state
diagram in Summit which produced code which would not synthesize. On
the other hand. Summit had better HDL import capability and some of
the experienced VHDL designers preferred the way Summit used libraries.
We have one seat of each currently and are going through a formal
assessment of them along with Renoir, looking at their capabilities
against user needs.
Generally, experienced VHDL users are not very receptive to the use of
graphical tools, except perhaps for doing complex state machine design.
Most will concede that it is a lot easier to share information if it
graphical than textual. Personally. I am for whatever one feels to be
the most effective. I advocate a mixed approach, with **overall**
productivity (which includes documentation and reuse) being the objective.
I consider HDLs as a means to an end, not an end in themselves. The ability
to easily switch between graphics and text or between languages is IMHO
the goal.
- John Vincent
Eastman Kodak Company Rochester, New York
---- ---- ---- ---- ---- ---- ----
> Let us be fair. I don't think Mentor targets professional asic
> designers with Renoir.
From: johne@vcd.hp.com (John Eaton)
Well they have certainly priced it for the professional asic designer.
I am a firm believer that for some areas of an asic that a picture is worth
a thousand words. So I have been looking for a good graphical entry tool but
have not been overly impressed with any of the current offerings.
You can do block diagram entry with any schematic capture package that
has verilog, vhdl or edif netlist output. I have to use schematic capture
anyway when I lay out test and product boards and it makes sense to use
the same system to create the top level of the chip.
So do they build their block diagram editors around existing schematic
systems that someone might already use? No they create a whole new tool
that you have to buy and learn.
Schematic capture packages at least let you define the shape of your symbols.
Some of these "block" diagram editors seem to think that any shape as long
as it's rectangular is fine. I would like to see these guys lay down a sheet
full of synopsys designware primitives using theirs tools that actually is
understandable.
ASIC designers are suffering from tool overload. We do not need more tools
that take more time to install and learn than they save.
- John Eaton
Hewlett-Packard
( ESNUG 289 Item 5 ) ----------------------------------------------- [5/98]
Subject: Making Custom Wire Load Models Without Floorplan Manager
> John,
>
> At SNUG'98 there was a lot of talk about making custom wire load tables
> without having Floorplan Manager. Do you know where I can get more
> information on that subject?
>
> - Shawn Hector
> Exar Corp.
From: jcooley@world.std.com (John Cooley)
Shawn,
Immediately after SNUG'98, I reposted Lee Bradshaw's article about how to
do this in ESNUG 284 #1. This article will tell you all you want to know.
- John Cooley
the ESNUG guy
( ESNUG 289 Item 6 ) ----------------------------------------------- [5/98]
Subject: ( ESNUG 288 #12 ) Want Testbench With Both Internal & Boundry Scan
> One of the feature I particularly appreciate is Test Compiler that gives
> me the possibility of synthesizing internal scan chains and boundary scan
> circuitry, compliant to 1149.1 JTAG standards. .... To be honest I still
> haven't obtained a test-bench that gives stimuli to the TAP pins: TCK,
> TMS, TRST and TDI, but only to the inputs of the scan chains. For the
> JTAG output TDO the testbench asserts that the value desired is 'Z' from
> the beginning to the end.
>
> - Davide Falchieri
> Bologna University Bologna, Italy
From: "Geoff Jones" <gjones@atl.com>
I've used the Synopsys generated boundary scan logic and it does seem to
work. One problem was that it insisted on routing 'observe only' input
signals through the capture boundary scan cell. (i.e The signal from the
pad was routed to the boundary scan register cell and then on to the core
instead of just branching off from a direct route from pad to core.) This
could have caused long delays on input signals if the boundary scan cells
were not placed in a good position.
The version of the Synopsys tools that I used did not make any test vectors
for the boundary scan circuit. I ended up writing a program in C++ that
parses the report file to create a model of the JTAG logic that can be
driven with commands like 'read idcode' and 'load_instruction extest'. This
made an ASCII file that I could use in a testbench to drive the gate-level
sim. It also predicted the output of TDO whenever it could. It also writes
out a BSDL description of the chip. If you really want to try some
home-made software e-mail me and I'll send you the files. (Works on HPUX
g++ and PC Visual C++).
- Geoff Jones
ATL Ultrasound
( ESNUG 289 Item 7 ) ----------------------------------------------- [5/98]
Subject: ( ESNUG 288 #2 ) VCS No Longer Waits For Licences? That SUCKS !!!
> The new rev. of now synopsys's VCS doesn't wait for a license any more,
> this ability allowed a larger number of users to use fewer licenses of VCS
> (queing theory) the runs which are started wait for a license then run.
> Now they fail saying "No license". I'm sure this increases the number of
> license needed by many eng. groups. More $$$ for Synopsys I suppose that
> they need to do this to get return on the 1/2 billion dollar cost of
> ViewLogic.
From: Don Reid <donr@hpcvcdo.cv.hp.com>
What some of us do for Design Complier is to run a small script which
scans the log file for the "No license" message. If found, it sleeps a
few minutes and trys again.
This sort of thing does little to affect sales, it just annoys customers.
- Don Reid
Hewlett-Packard
( ESNUG 289 Item 8 ) ----------------------------------------------- [5/98]
Subject: ( ESNUG 288 #0 & #3 ) The "Cooley Effect" & Ron Collett's Bad Advice
> Surprisingly, a positive opinion from you does NOT imply future success.
> Rather, the "Cooley Effect" predicts great success when you choose to
> criticize a company. So, I am respectfully asking (OK, begging), that you
> say something terrible about us. We don't care what, just say anything
> -- but keep it negative.
>
> - Kevin M. Bush
> VP Marketing
> MINC Incorporated
> Has Ron Collett ever been right about anything? One of Claude Shannon's
> theorems is that an information channel which is perfectly wrong transmits
> just as much information as one which is perfectly right. ... So, I always
> pay utmost attention to Ron Collett. I read his conclusions assiduously,
> and them act boldly, in complete confidence that whatever he predicted
> isn't going to happen.
>
> - Howard Landman
> Toshiba America Electronic Components
From: "Michael T. Horne" <mikeh@qualis.com>
If this is true, then we can predict great success for Ron Collett and
his market ramblings! Dear God, John, what have you done?!
- Michael Horne
CEO of Qualis Design
( ESNUG 289 Item 9 ) ----------------------------------------------- [5/98]
Subject: ( ESNUG 287 #5 288 #1) "Crack VMC & Win $75,000" Is A Rigged Bet
> I think I agree that, if the compiled model DOES NOT CONTAIN the info
> which is needed to reconstruct the source to the level required by the
> contest, then this is not only a sucker bet but also a red herring. It's
> a sucker bet because, it's like having a contest to decompile a C program
> where you can't win unless you recreate the original variable names - and
> where the binary has been stripped so that information isn't available.
> ... It's rather disingenuous to imply that only decrypting information
> which doesn't even exist constitutes "breaking" the encryption!
>
> - Howard Landman
> Toshiba America Electronic Components
From: "Rob Dekker" <robd@gowebway.com>
Hi John,
I'm Rob Dekker. Used to be director of engineering at Exemplar. Now, I'm
an indepenant consultant.
With some free time on my hand, I decided to take a look at the VMC contest.
Without a simulator, I went for the real thing: try to get the RTL code
back. I boldly digged into the compiled code. After three days, I got the
feeling that I'm tricked into an impossible task. This is compiled code,
and it looks like the references to internal signal names are not there.
I can only find port names. So how can I recover the RTL source? Is it
even possible? Or should I try to recover just the behavior? (Which is,
by the way, already a big challenge).
- Rob Dekker
Gowebway
---- ---- ---- ---- ---- ---- ----
From: Moe Shahdad <mshahdad@Synopsys.COM>
John,
I am the product manager for VMC, and I believe that Howard has raised a
number of interesting issues ( ESNUG 288 Item 1 ):
1. VMC does not strip any information, rather it converts the information
to a protected compiled form. Therefore, it is mathematically possible
to recover the source. However, we believe that this is a very difficult
task as it should be, and that's why you can win a Humvee. The primary
reason for this difficulty is that, unlike encryption, there is not a
one-to-one mapping between the source and target, i.e., there may be
many source constructs that match a given object construct.
2. With regard to the $18,000 prize, again all the information is present
in the object. Furthermore, this is a less difficult task because you
don't have to generate the equivalent source. You can use the data
sheet, the behavior of the model, and whatever you can extract from the
object code to create the original IP. This is a doable task, but
difficult.
With regard to needing years to solve the problem, that is exactly our
point. It is preferable to need years to break up a VMC object, rather
than years to litigate in the courts to win damages for unauthorized use of
IP. Hopefully, by the time a VMC object is broken the IP has run its
normal life cycle, and the owner has had the time to create new ones.
- Moe Shahdad
Synopsys VMC Marketing
[ Editor's Note: Go to http://www.synopsys.com/secureip if you want to
try your own hand at this code cracking contest. - John ]
( ESNUG 289 Item 10 ) ---------------------------------------------- [5/98]
Subject: ( ESNUG 287 #4 288 #9 ) Need 98.02 Ultra To Replace Old Commands?
> We're attempting to run 98.02 and have found an interesting requirement of
> another license (DC Ultra) in order to use one of the new commands that
> replaces an obsolete compilier option (prioritize_min_paths).
>
> set_cost_priority gives an error message.
>
> Has anyone else run into this problem?
>
> - Mark Fox
> Advanced Micro Devices
From: [ A Synopsys CAE ]
John,
The option "-prioritize_min_paths" in compile is still available for
backward compatibility. This option has not been removed or moved to
DC Ultra. With the new min/max optimization capability in Design
Compiler, there is less need to use the "prioritize_min_paths" option.
Thus, when you tried using it, the tool will generate a warning but
it will still optimize the design with min paths taken as a design rule.
This is to ensure that existing scripts using a 2-pass compile approach
for optimizing max and min separately will still work.
- [ A Synopsys CAE ]
( ESNUG 289 Item 11 ) ---------------------------------------------- [5/98]
From: Magnus Jacobsson <Magnus.Jacobsson@era.ericsson.se>
Subject: My Life Is A Living HELL Because Xilinx Has No Damn SCAN FF's !
Hi John,
We're working on a full-scan design where we're using the scan flip-flops not
only for test purposes, but also as a part of the functionality. In order
to verify parts of the design together with external hardware before we go
to silicon we're developing a prototype board with a Xilinx XC40125 FPGA
device.
A problem we have encountered is that we can't use insert_scan because there
are no scan flip-flops in the Xilinx library. Instead we have synthesised
the design to an ASIC library (lsi10k), performed scan insertion and then
reoptimized towards the Xilinx library. This works but gives quite some
area overhead which is very unfortunate since we're having problems fitting
it into the device. My question is if somebody have a better way of doing
this. Neither Synopsys or Xilinx have come up with a better solution.
People I've talked to have given me some suggestions:
1. Add a scan flip-flop to the Xilinx library. How do I do this?
2. Force Synopsys to create a mux in front of a normal flip-flop instead
of trying to use a muxed flip-flop from the library. A rumour says
that an earlier version of Synopsys did this and that it is possible
to force it into this "old mode". How do I do this?
3. Create a script that "manually" inserts the muxes and add appropriate
attributes in order for insert-scan to work. What attributes are
that and how should they be set?
If someone has done this before or have any other ideas on how to do it I'd
appreciate if you could share them on ESNUG.
- Magnus Jacobsson
Ericsson Radio Systems Kista, Sweden
( ESNUG 289 Item 12 ) ---------------------------------------------- [5/98]
Subject: ( ESNUG 287 #7 ) DC 98.02 Screwy Timing w/ LSI Logic lcbg10p Lib
> We came upon a bug in 1998.02 using the LSI Logic lcbg10p library. DC
> doesn't see the correct timing while optimizing, therefore it doesn't
> give good results for timing. Later when report_timing is done the
> correct timing shows up. It has something to do with min cap in the lib.
>
> - Paul LaBerge
> Micron
From: [ A Synopsys CAE ]
John,
There was a problem in DC with designs using set_min_capacitance, set_load
-min, or set_wire_load -min, or if a min_capacitance constraint existed in
the technology library. An internal variable was reset to an incorrect
value, which caused compile to use an optimistic delay cost. This problem
could result in some timing violations not being optimized. This problem has
been fixed in the 1998.02-1 release.
- [ A Synopsys CAE ]
( ESNUG 289 Item 13 ) ---------------------------------------------- [5/98]
From: Victor_Duvanenko@truevision.com
Subject: How Can I Test Embeded RAMs Via The Full SCAN Chain Automagically?
John,
I'm curious if anyone in the chip CAD market can test the embeded RAMs
through the full scan chain. Are there any EDA products/tools that do this?
Theoretically, you should be able to accomplish this since there are
Flip-Flops all around the RAMs, which the scan chain has complete control
over. Plus, I don't really care how many vectors it takes, as long as the
process is automagic.
- Victor J. Duvanenko
Truevision
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