( ESNUG 341 Item 6 ) --------------------------------------------- [1/26/00]
From: Georg Zehentner <zehentner@heidenhain.de>
Subject: What's The Customer Dirt On ModelSim's Verilog/VHDL Co-Simulation?
Hi John,
We're thinking about using Modeltech's ModelSim to simulate a Verilog gate
level design in a VHDL-Testbench. (We want to reuse the VHDL testbench we
designed together with the Verilog RTL code of the design.) I'm interested
in any user experiences with ModelSim's Verilog engine & their VHDL/Verilog
co-simulation. How about their:
- Simulation time ( especially for designs about 100k gates)?
- Compile time ( especially for designs about 100k gates)?
- Backannotation (again, for 100k gates)?
If someone has experiences compared to Verilog-XL or Synopsys's VCS or
Viewlogic's Fusion, it would be great. Many thanks for moderating the
ESNUG, John.
- Georg Zehentner
HEIDENHAIN GmbH
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