| # |
Date |
Description |
Size |
Download? |
| #71 |
03/2016 |
Igor Keller of Cadence R&D warns non-Gaussian distributions haunt below 16/14nm in ESNUG 558 #12.
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18 pages
518 kB
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| #70 |
05/2015 |
The Mentor-Tanner marketing whitepaper MENT distributed right after the merger in ESNUG 550 #7.
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6 pages
1.69 MB
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| #69 |
10/2014 |
Consultant Luis Basto using Cadence cell-aware ATPG with Freescale back in 2007 in ESNUG 538 #12.
|
10 pages
193 kB
|
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| #68 |
04/2013 |
Cadence v BDA complaint 3:13-cv-01539 filed on April 5th in California Northern District Court in ESNUG 510 #9.
|
9 pages
288 kB
|
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| #67 |
05/2012 |
Horace Chan and Jeffrey Huang of PMC-Sierra CDNlive'12 paper on Palladium and Specman "e" in ESNUG 505 #7.
|
23 pages
472 kB
|
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| #66 |
04/2012 |
Mike and Avidan's DVcon'12 paper plus the Mentor eRM to UVM Migration Kit in ESNUG 502 #5.
|
15 pages
319 kB
|
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| #65 |
11/2011 |
The Azuro Rubix/CCOPT whitepaper paper as referenced in ESNUG 495 #9.
|
20 pages
497 kB
|
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| #64 |
04/2011 |
The Si2 UPF CPF analysis paper as referenced in ESNUG 490 #9 by Bill Bayer.
|
70 pages
270 kB
|
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| #63 |
04/2010 |
The Cadence EDA360 "Vision Paper" that CDNS is proposing to grow EDA from $5 billion to $25 billion as referenced in Wiretap 100430 by John Bruggeman.
|
32 pages
696 kB
|
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| #62 |
02/2009 |
The paper detailing ac_datatypes for verification and synthesis in ESNUG 479 #4.
|
6 pages
48.3 kB
|
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| #61 |
07/2007 |
Mike Meredith's research that Aart de Geus, Wally Rhines, and Rajeev Madhavan have been quietly trying to suppress from ESNUG 467 #16.
|
2 pages
18.6 kB
|
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| #60 |
03/2007 |
E-Tools open source CCS-to-ESCM library translator from ESNUG 464 #6.
|
45 files
843 kB
|
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| #59 |
02/2007 |
George Harper's Bluespec design challenge entry from ESNUG 459 #5.
|
139 files
1.68 MB
|
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| #58 |
05/2005 |
Danny Traynor's eval of the FishTail Focus tool from ESNUG 445 #4.
|
15 pgs
73 kB
|
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| #57 |
03/2003 |
"ESNUG Guideline For Mentor Employees" (Author Unknown)
|
6 pgs.
14 kB
|
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| #52 |
10/2003 |
Hari Krishnan's 2003 Magma Users Group paper on Magma's design flow
along with Ajay Daga's paper on FishTail's Magma design flow.
|
1.04 MB
581 kB
|
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| #51 |
10/2003 |
Sandeep Mirchandani's 2003 Magma Users Group meeting paper on "Hacking
Magma for Fun & Profit" from ESNUG 420 #6.
|
29 pgs
1.37 MB
|
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| #50 |
08/2003 |
Howard Landman's old SNUG'98 and new Magma 2003 synthesis area vs. delay "banana curve" papers as mentioned in this Industry Gadfly column.
|
2.58 MB
|
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| #49 |
09/2002 |
Michael Esty's Cadence Analog Artist & Nassda HSIM mixed-signal
methodology paper from the 2002 Cadence User Group meeting (as mentioned
in ESNUG 416 #7.)
|
14 pgs
471 kB
|
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| #48 |
05/2003 |
Doug Bailey's Altera Cyclone vs. ASIC business comparison from ESNUG 413 #5.
|
3 pgs
7.6 kB
|
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| #47 |
05/2003 |
Mark Indovina's FPGA vs. ASIC worksheet from ESNUG 413 #5.
|
2 pgs
15 kB
|
View
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| #46 |
12/2002 |
Saeed Coates and Jason Chun's very detailed user review of @HDL @Verifyer 2.8 from ESNUG 413 #1.
|
35 pgs
602 kB
|
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| #45 |
11/2002 |
Joe Rodriguez's app note on speeding up ModelSim 5.7 SE runs from ESNUG 412 #14.
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16 pgs
358 kB
|
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| #44 |
10/2002 |
Matt Weber's Boston SNUG'02 On-Chip Variation (OCV) paper & slides as mentioned in ESNUG 411 #2 and hinted at in ESNUG 411 #1.
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189 kB
|
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| #43 |
04/2003 |
Rajesh Bawankule's DVcon'03 paper & slides in ESNUG 410 #8 that teaches you how to get fast Verilog runtimes at no cost.
|
514 kB
|
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| #42 |
04/2003 |
Dan Joyce's first place DVcon'03 paper & slides on how to reduce corner case testing in your random vectors from ESNUG 410 #7.
|
163 kB
|
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| #41 |
03/2003 |
Don Mills and Cliff Cummings' paper on asynch vs. synch resets in multi-clocked designs from ESNUG 409 #11.
|
238 kB
|
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| #40 |
03/2003 |
An update of Cliff Cummings' Non-Blocking Assignments paper that now also discusses the effect of #1 delays in Verilog simulations from ESNUG 409 #10.
|
279 kB
|
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| #39 |
10/2002 |
Pallab Chatterjee & Rick Kelly's Magma User Group papers from ESNUG 402 #7.
|
2.69 MB
|
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| #38 |
02/2003 |
Steve Ehlers' Lazyman (lman) generic EDA tool man page script from ESNUG 406 #2.
|
2.6 kB
|
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| #37 |
02/2003 |
Jeff Winston's seven different freebie tools from ESNUG 406 #4.
|
47.8 kB
|
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| #36 |
07/2002 |
Kevin Croysdale's graphical Perl script for PhysOpt and DC logs from
ESNUG 396 #13.
|
1.2 MB
|
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| #35 |
01/2003 |
David Simmons' hold fix DC scripts that clean up the hold time buffering on scan chains from
ESNUG 404 #5.
|
4.8 kB
|
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| #34 |
11/2001 |
Kris Monsen's quickie tutorial on using CVS (in response to ESNUG 383 #11.)
|
5.9 KB
|
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| #33 |
09/2001 |
Rick Furtner's paper on synthesizing high fanout nets in Design Compiler (from Boston SNUG'01.) A useful paper for DC users.
|
26 pgs
86 KB
|
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Download
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| #32 |
03/2002 |
Tom Fitzpatrick's 86 page Superlog intro tutorial plus David Rich's
107 page advanced Superlog tutorial (both from HDLcon'02)
|
193 pgs
2.2 MB
|
Download
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| #31 |
09/2001 |
Jason Ware's updated Synopsys synthesis checklist. (See Download #2 below.)
|
7 pgs
43 KB
|
View
Download
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| #30 |
02/2002 |
Kazutaka Murakami's initial eval of the new Avanti Astro P&R tool (from
the 2002 Avanti User Group meeting.)
|
13 pgs
404 KB
|
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| #29 |
04/2002 |
Jens Michelsen's scripts that he used in his initial eval of Synopsys Clock Tree Compiler (ESNUG 393 #9)
|
2 pgs
1.4 KB
|
Download
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| #28 |
03/1999 |
Steve Golson's award winning "Resistance Is Futile!" SNUG'99 paper. It
outlines how to build better wireload models.
|
18 pgs
1.4 MB
|
Download
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| #27 |
11/2000 |
Two PDFs on the optimal library to use with DC-Ultra. One old PDF and one newer PDF. (In response to ESNUG 360 #5.)
|
14 pgs
6 pgs
|
View Old
View New
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| #26 |
06/1999 |
Alessandro Fasan's paper about translating 60,000 lines of VHDL to
Verilog in 3 man-months using ASC's VHDL2Verilog translator and Formality as an equivalence
checker. (In response to ESNUG 341 #10.)
|
28.9 KB
|
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| #25 |
08/2000 |
Volker Rzehak's scripts that solve the "opposite enable tri-state buffer"
problem as described in ESNUG 356 #1.
|
8.2 KB
|
Download
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| #24 |
02/2001 |
David Gregory's Avanti hierarchical flow talk. (He was doing a 500 K inst design.) This won best paper at
the 2001 Avanti User Group meeting.
|
414 KB
|
Download
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| #23 |
05/2001 |
Bill Lenihan's Synplicity bug list and Synplicity wish list. This came from Greg Arena complaints about Synplicity's technical support in ESNUG 370 #10.
|
11.7 KB
|
View Bugs
View Wishes
Download
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| #22 |
06/2001 |
Paul Zimmer's Vim syntax file for PrimeTime.
|
10.3 KB
|
Download
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| #21 |
03/2001 |
The memo from Synopsys Corporate to the Synopsys Physical Synthesis Staff. Here they admit the serious user problems with Chip Architect and introduce "Hidden Dragon" as a fix.
|
2 pgs.
5.8 KB
|
Download
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| #20 |
03/2001 |
Bob Wiegand's DC Area & Timing papers from SNUG'01. (See his MIN/MAX SNUG'99 paper, too, because this paper builds upon it.)
|
17 pgs.
45.1 KB
|
Download
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| #19 |
03/1999 |
Bob Wiegand's SNUG'99 MIN/MAX DC tricks paper. (
SNUG'99 #28)
Neat stuff!
|
19 pgs.
72.1 KB
|
Download
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| #18 |
03/2001 |
Here's how to mix old and new Synopsys DC, VCS, PrimeTime, (or whatever) licenses. (Useful if you're re-working legacy designs.)
|
10 pgs.
23.8 KB
|
View
Download
|
| #17 |
03/2001 |
An anon engineer's fix to the Avanti PDEF 2.0 <-> PhysOpt PDEF 3.0 interoperability problem. Also read Andy Pagones' modifications in ESNUG 368 #2.
|
38.2 KB
|
View
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| #16 |
03/2001 |
Paul Zimmer's (of Cisco) award winning SNUG'01 paper on all sorts of clever tricks using PrimeTime. This exceptional paper won first prize at the conference.
|
225 KB
|
Download
|
| #15 |
03/2001 |
Steve Golson's 2nd place SNUG'01 paper benchmarking & comparing 7 different
hierarchical synthesis techniques (covering everything from default DC runs
to compile_simple_mode to ACS pass0 through pass2.) A damn good paper!
|
12 pgs.
95.8 KB
|
View
Download
|
| #14 |
03/2001 |
Cliff Cumming's award winning (3rd place) SNUG'01 paper on synthesizing multi- asynchronous clocks. Real world problems with metastability between different clock domains and FIFO issues are discussed in great detail here.
|
26 pgs.
168 KB
|
View
Download
|
| #13 |
03/2001 |
The SNUG'01 slides from Chris Malachowsky of NVidia discussing all sorts of
details involved with developing large chips. (There's a lot of
real world project data buried in these slides. A rare find!)
|
4.65 MB
|
Download
|
| #12 |
02/2001 |
Dan Joyce of Compaq's HDL Con'01 paper describing his
experiences doing C-based design using C-Level's System Compiler. (See also ESNUG 357 #12.)
|
8 pgs.
74.8 KB
|
View
Download
|
| #11 |
02/2001 |
The HDL Con'01 slides from Dan Joyce (of Compaq) describing his company's
experiences doing C-based design using C-Level's System Compiler. (See also ESNUG 357 #12.)
|
1.02 MB
|
Download
|
| #10 |
02/2001 |
Dave Rich's Superlog tutorial from HDL Con'01. See what everyone talking about.
|
126 pgs.
1.27 MB
|
Download
|
| #09 |
10/2000 |
Gregg Lahti's & Tim Wilson's "Tcl Oriented Procedural Synthesis (TOPS)" environment from the Boston SNUG 2000 conference. This download includes a
paper on DC-Tcl gotchas, too.
|
342 KB
|
Download
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| #08 |
04/1999 |
Erich Whitney's DC-Tcl Tutorial from SNUG'99 -- an excellent tutorial for Tcl newbies.
|
68 KB
|
Download
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| #07 |
10/2000 |
Erik Olson's & Tim Wilson's "Hierarchy Surfer" from Boston SNUG 2000.
|
62 KB
|
Download
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| #06 |
09/2000 |
Barbara Heninger's Cadence "OpenBook vs. CdnSrc" HTML comparison as described in ESNUG 359 #02.
|
3 KB
|
Download
|
| #05 |
08/2000 |
Synopsys PDF doc on their unreleased "Presto" rewrite of HDL Compiler (ESNUG 357 #04)
|
141 KB
|
Download
|
| #04 |
01/2000 |
Jeff Winston's "IPOfix" buffer resizing program (
ESNUG 339 #01 and
341 #03).
This C program takes the PrimeTime output of your chip and speeds up all the slow gates in your design's paths that are failing timing.
|
63 KB
|
Download
|
| #03 |
01/2000 |
Janick Bergeron's "vrhfix" script to fix the Vera "Missing Classes"
problem (ESNUG 341 #15)
|
2 KB
|
Download
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| #02 |
11/1999 |
Jason Ware's "Successful Synthesis Checklist" -- a detailed checklist useful for
anyone doing synthesis with Design Compiler. (Often a good idea to print out
and manually check off while synthesizing.) (See Download #30 above.)
|
34 KB
|
Download
|
| #01 |
04/1999 |
Jeff Johnson's technically meaty "High Performance Synthesis For DC" paper.
This gives you all the known tips and tricks used to get the best, highest speed
or lowest area synthesis (WLM) results from Design Compiler.
|
40 KB
|
Download
|
