( ESNUG 370 Item 5 ) -------------------------------------------- [05/17/01]
Subject: ( SNUG 01 #23 ) NDA "Ketchum" Found Along With DW_16550 UART Bugs
> The new gossip on Ketchum is that Moto (Austin) and possibliy ST Micro
> (Agrate, Italy) are doing the 1st round of alpha testing. I'm told that
> the way Ketchum works is Ketchum thinks for about 12 hours on your design
> and then spits out a Verilog stimulus file. That Verilog file runs for
> 2 minutes in your chip's test suite and, voila!, you have 100% functional
> coverage (or not.) The actual Ketchum runtimes range from minutes to
> infinity. It's *very* alpha. Ketchum uses a Synopsys proprietary
> assertion language that's made to work with VCS, Scirroco, Vera, and
> CoverMeter. (This assertion language may be opened by Synopsys later.)
> Synopsys tells the Ketchum customers that the DW team is using Ketchum
> for its internal DW development, but I don't know if that true or not.
>
> - from the SNUG'01 Trip Report
From: Vladimir Sindalovsky <sindalovsky@agere.com>
Hi, John,
Recently I encountered the Ketchum tool you mentioned in your SNUG'01 Trip
Report. We were using DW_16550 UART in our design, and during usual
simulation process, I uncovered few functional bugs. We were close to
the tape out, so the situation was very tense, but, luckily, Synopsys's
designers came up with a quick fix. It would be better not to have bugs
in Synopsys DW IP at all, but "nobody's perfect".
Some time later I received from Synopsys some additional bug reports for
such subtle bugs that I got really interested how they were found. (An
example being the report stated that if a character is received exactly
one clock period after the status register polling, the data ready flag
won't be generated. This kind of bug is often missed during verification
and fixed later by software workarounds.) The Synopsys guys mentioned to
me their internal formal verification tool (Ketchum?) allowed them to verify
the DW design. They said they'll be broadcasting all these DW_16550 bugs
to customers next week. I still don't know how much effort the creation
of a formal description takes. Maybe somebody else had an encounter with
Ketchum (alfa testing participants?)
- Vladimir Sindalovsky
Agere Systems
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