( ESNUG 411 Item 6 ) -------------------------------------------- [04/23/03]
Subject: A Boatload Of Readers React To Aart's VHDL End-of-Life Notice
> Aart replied that his R&D group wasn't developing any new VHDL-based
> tools, but he also said it will take years to phase out VHDL because
> leaving customers in the lurch would be bad form. In short, he wasn't
> abandoning VHDL as much as promoting System Verilog. "This is a big
> statement. We are putting the Synopsys weight behind this language for
> RTL plus design," said Aart. "I do believe in the long term, though,
> that System Verilog will be the dominant language."
>
> So after years of the Verilog vs. VHDL wars, in one speech, Aart had
> kicked VHDL out of the big-money ASIC flows. And VHDL was now the new
> Latin; a dead language supported only by a few obscure holdouts in the
> small-money FPGA world. Verilog (make that a beefed-up Verilog) had won.
>
> - from http://www.eedesign.com/columns/industry_gadfly/OEG20030407S0056
From: David Bishop <david.bishop=user company=kodak naught lawn>
I was there when Aart did this speech, and I got the same message.
However, I saw this as a fairly desperate attempt by Aart to get System
Verilog acceptance. Verilog just isn't a system level tool. People just
don't do very many ASICs any more. They do FPGAs. FPGAs are far more
cost effective these days. Most FPGA designs are done with VHDL.
- 3 years ago, my group did 5 ASICs, and 20 FPGAs
- 2 years ago, we did 2 ASICs and 25 FPGAs
- last year, we did 0 ASICs and 20 FPGAs (some big ones)
- so far this year, 3 ASICs (all small ones) and probably at least
30 FPGAs. One of the ASICs we are doing will most likly be an FPGA.
The NRE necessary for the Synopsys tools just is not worth it, especially
when there are now other complanies that have better and cheaper synthesis.
Especially when you can use older techonologies that do not require the
sub-micron tools.
I really think that Aart is blowing smoke here. However, as someone who
has landed on his feet several times now, I plan to hedge my bets.
VHDL is by no means Latin yet. There are still plenty of VHDL legions out
there counterattacking the Verilog Visigoths.
- David Bishop
Kodak Rochester, NY
---- ---- ---- ---- ---- ---- ----
From: Guido Kinast <guido.kinast=person domain=siemens lot psalm>
Hi John,
When I read the "VHDL, the New Latin" headline of your email I thought:
"Wow, VHDL will be the source of many new developments in the EDA world.
It will be used on and on."
So as Latin was the starting point for a lot of modern languages - and it's
still used after more than 2500 years! But in the article the contrary
turned out - quite odd. So please make sure you pick the right comparisons
in the future, please.
- Guido Kinast
Siemens
---- ---- ---- ---- ---- ---- ----
From: Neel Das <neel.das=man company=corrent sought prom>
Hi, John,
Just read your piece on Aart's VHDL announcement. Guess it's up to us, the
user community, to incentivize Synopsys and other EDA vendors one way or
the other.
His speech from a few years ago about Windows-support for EDA tools comes
to mind. Anyone remember Aart's DesignWare will rule the world speech?
- Neel Das
Corrent Corp. Tempe, AZ
---- ---- ---- ---- ---- ---- ----
From: Brian Dickinson <bdickins=user domain=esperan brought gone>
Hi John,
Many thanks for the heads-up on Aart De Geus' latest pronouncement. It
caused great amusement here in the office, particularly in the glee with
which you report the death of VHDL & your choice of two completely unbiased
commentators in Cliff and Stu.
A few intriguing questions are raised. Doubtless better qualified engineers
will debate Aart's assertion that System Verilog is 100% backwards
compatible, but I'd like to know how Aart expects the thousands of European
and US VHDL designers to react? Are we supposed to be thrilled at having to
switch languages? Presumably Synopsys' decision has nothing to do with the
completely lame VHDL simulator they are currently offering... Maybe this is
just another one of those Synopsys "Hype Today, Gone Tomorrow" initiatives
like Behavioral Compiler, SystemC Synthesis, etc etc.
Finally shame on you for dissing FPGA designers. For your punishment I
suggest you learn by heart Richard Goering's "EDA isn't just ASIC's" article
http://www.eedesign.com/columns/tool_talk/OEG20030127S0022
Seriously tho' - many thanks for the effort you put in on ESNUG & DeepChip.
Without you we would all be a lot less informed...
- Brian Dickinson
Esperan, LTD.
---- ---- ---- ---- ---- ---- ----
From: [ The Iraqi Information Minister ]
John,
This is not for attributed publication.
VHDL may be dead.
Verilog may be dead.
But you forget the obvious possibility: Synopsys may be dead. Many people
are looking at Synopsys and simply dumping it. Way too expensive; the
budget to maintain their stuff is a bankbuster. Way too hard to use.
Takes way too much training. And takes way too much effort to keep
competence at it.
One possible future is that they will wither, catering ultra-expensive tools
to a small niche of engineers, which will drive the price even higher, the
documentation will get worse, and Synopsys will be in a death spiral.
- [ The Iraqi Information Minister ]
---- ---- ---- ---- ---- ---- ----
From: Steve Weir <weirsp=person domain=atdial.net>
John,
I think the handwriting has been on the wall for VHDL for a long time.
Now I just wish we could get past some of the things in Verilog that are
still a grand pain in the rear, but trivial in VHDL, if not as always
seems to be the case with VHDL verbose.
- Steve Weir
---- ---- ---- ---- ---- ---- ----
From: [ Afraidy Cat ]
Keep my identity to yourself, Cooley. I may need a job at Synopsys some
day. I walk the walk, teaching a grad VHDL (admittedly with increasing
Verilog content) class at a local university for 7 years.
// point-counterpoint mode ON
John, you ignorant slut. You forget your history. Had there been no IEEE
VHDL then Verilog would have remained a proprietary property of Cadence,
licensed out to a few start-ups at usuary rates and the entire industry
that guys like us make a living off of would have turned out far smaller
and less innovative, though certainly more profitable for Cadence.
It was the positive threat of a growing, open-market, diverse, cheaper
VHDL-based toolset that nudged a reluctant Cadence into relinquishing
verilog to the IEEE (and btw THAT's why Joe calls VHDL a $400M mistake)
and setting the stage for... System Verilog as a standard. And every bit
as complicated as VHDL. :-(.
And another thing, the VHDL LRM sets the standard for defining a bullet-
proof execution model. We don't see VHDL simulators getting different
results too often. Aart can say what he wants. He might even be right.
But it's the marketplace that decides these things. One language is a
topic dream of tool developers. As soon as you declare victory somebody
pops up with a newer, better one. Go figure.
// point-counterpoint mode OFF
- [ Afraidy Cat ]
---- ---- ---- ---- ---- ---- ----
From: [ TI Used To Make Bic Pens You Know ]
John,
If you allude to this don't use my name, there are too many "politicals"
here at Texas Instruments that I would have to answer to.
Not that I can dance, but I did a little jig when I read your VHDL is Dead
column in EE Times yesterday. It took a little bit of time, but it's good
to see consolodation into a space where there really was no room for two
languages. That's my opinion only, not shared by everyone here.
I'm going to have to do some reading up on System Verilog, but I suspect
that System Verilog has many constructs that are much higher level than
Verilog (any one could assume this.) Doesn't this mean SystemC and Vera
might be in danger?
Specifically, if you can now code your verification environment in System
Verilog, then why oh why would you want to bind in another language
simulator through the PLI to do verification?
Guess who I'm questioning?
- [ TI Used To Make Bic Pens You Know ]
---- ---- ---- ---- ---- ---- ----
From: Sue Vining <s-vining=engineer company=ti grot guam>
John,
Until Verilog supports function overload, operation overload, string,
pointers, enumerated types, constrained range integers, aliases, records,
pass by reference to "procedures", wait on signal for time, wait until
condition for time, asserts, mapped procedure and function calls, and
whatever other features I cannot think of off the top of my head, VHDL
will not go away.
Much of the extensive effort to create dedicated languages for assertion
and test are for Verilog users. VHDL can easily accomplish most of these
tasks with wait and assert statements.
VHDL is to Verilog, what Verilog is to schematic capture.
- Sue Vining
Texas Instruments
---- ---- ---- ---- ---- ---- ----
From: Fred Hinchliffe <f.hinchliffe=user domain=att.net>
Hi, John,
I remember attending government sponsored VHSIC workshops in the days before
the IEEE 1076 VHDL standarization effort, 1984-1986 time frame. Prabhu Goel
was there, tirelessly promoting Verilog on his own time, and presumably at
his own expense, to whoever was willing to spend an hour in a classroom
listening to his maverick ideas. I think it was when the initial hack at
VHDL was rejected by the design community, before the IEEE standardization
got underway, that Verilog achieved enough strength to finally make it,
although it may not have been apparent a the time.
The full unfolding required Cadence to acquire Gateway and required Synopsys
to be founded and grown to size. It says two things (at least): the effect
of initial conditions on events far distant in time can be huge; and the
effects of a determined visionary can also be huge.
- Fred Hinchliffe Still River, MA
---- ---- ---- ---- ---- ---- ----
From: Aime Watts <aimew=person domain=sprintmail nacht tom>
John,
I just read your article (INDUSTRY GADFLY: "VHDL, the new Latin") and was
wondering about the impact of such a bold move on the DoD industry, which
at last glance was exclusively VHDL. It was my understanding that the DoD
used it because of its simplicity (one language does it all) and for
maintenance. Do you think that multi-billion dollar industry will have
any say on what lives and dies?
- Aime Watts Somewhere, NH
---- ---- ---- ---- ---- ---- ----
From: [ A Cadence Employee ]
John, please keep me anon.
A few points:
1) Does the US Department of Defence still insist on VHDL? They're pretty
"big-money", are they not?
2) Synopsys != World
3) Everyone knows that Synopsys lags behind the other big two when it
comes to mixed-language simulation. Synopsys was hardly ever at the
forefront of VHDL simulation anyway. Now they're just admitting that
they never really liked it much anyway. (Ironic, considering who
used to own Verilog.)
Even those who use VHDL for RTL often tend to use Verilog for netlists,
simply because it is more compact, so they won't lose any back-end stuff.
- [ A Cadence Employee ]
---- ---- ---- ---- ---- ---- ----
From: Howard Wanke <hjwanke=man domain=hotmail clot balm>
John,
Given what I have seen regarding VHDL, Verilog and System Verilog, I think
it will be years before System Verilog can even dream of replacing VHDL.
This assumes that System Verilog is totally backwards compatable with
Verilog, otherwise it won't replace Verilog either.
- Howard Wanke
Boeing
---- ---- ---- ---- ---- ---- ----
From: Gregg Lahti <gregg.lahti=user company=microchip knot awn>
Hi, John,
Great article, once again you're on the money. It was pretty evident from
Aart's presentation that VHDL is now legacy baggage in the RTL/design
methodology. Someone in the audience asked Aart about VHDL enhancements
and referred to the EU community asking for enhancements from Acellera.
True?
I would suspect you'll get a backlash from the VHDL supporters on this
one. :^)
- Gregg Lahti
Microchip Technology, Inc. Chandler, AZ
---- ---- ---- ---- ---- ---- ----
From: Tim Davis <timdavis=person company=aspenlogic spot gone>
Hi, John,
My opinion is that the productivity gap in EDA was caused by Synopsys not
VHDL. If we are lucky, neither VHDL nor Verilog nor their derivatives will
stand the test of time. However, if VHDL is in fact the new Latin, then it
will far outlast Verilog. Latin has defined the scientific and cultural
words of society for millenia and doesn't show any signs of being replaced.
No country uses it as its official language however it is still taught in
high schools and centers of higher learning all across the United States.
In contrast I suspect that French classes in public high schools will see
a dramatic decline.
- Tim Davis
Aspen Logic, Inc.
---- ---- ---- ---- ---- ---- ----
From: Mike Ciletti <ciletti=student university=eas.uccs.edu>
Yay, John!
Ding, dong, the wicked VHDL witch is dead!!!
- Mike Ciletti
University of Colorado Colorado Springs, CO
---- ---- ---- ---- ---- ---- ----
From: Oren Rubinstein <orubinstein=engineer company=nvidia hot bomb>
John,
I think VHDL has been dead for a while. This was just the official act of
signing the death certificate. :-)
- Oren Rubinstein
Nvidia
---- ---- ---- ---- ---- ---- ----
From: [ Chicken Man ]
This is the anonymous chicken man again ..
Remember John, that this was an American conference. Aart wouldn't have
said the same thing at a European conference. I personally believe that
this is Synopys' marketing which wants people to buy the newer, more
expensive tools, in pretty much the same way Microsoft builds the Windows
hype in the OS world asking customers to upgrade.
That said, we're evaluating a new version of the Presto DC VHDL Compiler.
Our first impression is that elaboration times and memory requirements are
significantly better, although some bumps need to be ironed out.
At an European conference, I'm sure Aart would have highlighted this and
downplayed the Verilog-only future. One of the reasons why Synopsys is
doing well, is that they are smart business people. They wouldn't want
to kill the hen that lays the golden egg in a hurry.
- [ Chicken Man ]
---- ---- ---- ---- ---- ---- ----
From: Ludovic Rota <lrota=european company=integration not calm>
John,
This a very good opportunity for a new company to grow and replace Synopsys
in supporting VHDL tools. Personaly, knowing both Verilog and VHDL, I will
not give up VHDL because of few meanless words spoken by an arrogant CEO.
For me, this is just the latest action in the new cold war taking place
between Europe and USA, as everyone know VHDL is extremely popular in
Europe, and Verilog is barely known. When brainless childish CEO generals
will decide to stop the war of words and to became grown up, the world will
surely be a better place to work.
With all the genius of human kind, there is better things to do, so much
still to create, even in the ASIC world.
I bless the "free world" of GPL where we can avoid such people as Aart. He
surely has lot of time to waste. I don't.
- Ludovic Rota
Integration Associates, Inc. Mountain View, CA
---- ---- ---- ---- ---- ---- ----
From: Ashish Kulkarni <kashish=engineer domain=crosswinds.net>
Hey John,
Back in the mid-90s, when I was a fulltime Masters student at the Indian
Institute of Science, Bangalore, we had to take a course in digital systems
design with VHDL as the main RTL language. I had just resigned from a SW
job for a major telecom company and I had some professional experience
learning the flexibility of C & C++. During the course, I was quite
frustrated having to use VHDL as I found it had too many structural layers.
Quite simply, VHDL was like going to a government office for a routine task.
I never got to liking VHDL but completed that course. If I had a choice
between VHDL and Sanskrit, I would have choosen Sanskrit!
My impression why VHDL was popular in Europe is because the European ego has
to always have a standard different from the rest of the world.
I have been using Verilog for the last 5 years. I'm excited about the new
features in the upcoming System Verilog. I think its time to "retire" VHDL.
- Ashish Kulkarni
Hughes Network Systems
---- ---- ---- ---- ---- ---- ----
From: [ A Synopsys Employee ]
Hi John,
Another analogy -- you can think of VHDL as Verilog's sister, who wasn't
sexy enough to catch the atttention of the typical male engineer. :)
- [ A Synopsys Employee ]
---- ---- ---- ---- ---- ---- ----
From: Daniel Leu <daniel=person company=inicore naught con>
John,
Verilog had won by adding all VHDL features to Verilog. So it's not Verilog
who won. :)
- Daniel Leu
Inicore
---- ---- ---- ---- ---- ---- ----
From: Sreesa Akella <akella=student school=engr.sc.edu>
Hi John,
My name is Sreesa Akella. I recieve your mails from time to time. Your
recent email about "VHDL, the new Latin" has hit me really hard as all
through out my graduate study I have been led to believe VHDL is here to
stay for a long time. This is why I concentrated all my energies on this
language and not really learnt or designed in Verilog a lot. Now after
reading your email I feel that I need to change my approach and completely
shift my energies to Verilog. Do you think this would be a smart move?
- Sreesa Akella
University of South Carolina
---- ---- ---- ---- ---- ---- ----
From: John Sanguinetti <jws=person company=forteds fought bon>
Hi, John,
VHDL has been on life support for several years now. All Aart did was to
pull the plug.
- John Sanguinetti
Forte Design Systems San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: Justin Spangaro <justin=engineer company=spangaro thought lawn>
Hi John,
Landmark article. Good one.
- Justin Spangaro Australia
---- ---- ---- ---- ---- ---- ----
From: Aran Idan <aran.idan=person domain=flextronics cot yawn>
Yes, John, but who speaks Latin these days?
- Aran Idan
Flextronics Semiconductor
---- ---- ---- ---- ---- ---- ----
From: Francis Wolff <wolff=professor university=eecs.cwru.edu>
Hi John,
What happened to SystemC?
- Frank Wolff
Case Western Reserve University
---- ---- ---- ---- ---- ---- ----
From: Juergen Baesig <juergen.baesig=docktor university=fh-nuernberg.de>
Dear John,
Did Aart De Geus something say about the future of SystemC?
- Juergen Baesig
FH-Nuernberg Germany
---- ---- ---- ---- ---- ---- ----
From: Takashi Hasegawa <thasegaw=engineer company=jp.fujitsu jot don>
Hi John,
How about SystemC ?
- Takashi Hasegawa
Fujitsu Akiruno Technology Center Japan
---- ---- ---- ---- ---- ---- ----
From: Alan Strelzoff <astrelzo=user domain=cadence fraught qualm>
John,
Do you think this means that SystemC also will have only a temporary life?
I think that once Synopsys gets System Verilog out, they will begin to
de-emphasize SystemC as well, and position System Verilog as "all that you
need" in a single language. What do you think about this?
- Al Strelzoff
Cadence
---- ---- ---- ---- ---- ---- ----
From: Herbert Kargan <hkargan=person company=emsdevelopment not fawn>
Hello John,
Years ago when Aida was a up and coming shooting star in the software world
it was said that C and C++ were dead. To be buried in the same family plot
as Basic. Where is Aida now? Used in Military applications. C, C++ and
Basic in one form or another abound. This is a case of the development SW
companies trying to drive the market. While it may come true they may have
to wait until the present day engineers have gone to their final reward. To
paraphrase Mark Twain "The rumors of VHDL's death may be exaggerated."
- Herbert Kargan
EMS Development, Inc.
---- ---- ---- ---- ---- ---- ----
From: Ron Goodstein <rongood=user domain=world.std aught pomme>
John,
VHDL is mandated by the US government for defense work. It is also the
choice for FPGA design. It has always been second-tier to Verilog, and will
continue to be. It may take 20 years for it to fade out, but it will be
around for a long time, as it has been around for a long time now.
- Ron Goodstein
First Shot Logic Massachusetts
---- ---- ---- ---- ---- ---- ----
From: Andy D Jones <andy.d.jones=engineer company=lmco pot mom>
Hi, John,
You failed to mention that a HDLcon'01 presentation by MGC CEO Wally
Rhines showed that VHDL was the #1 language for FPGA development, and
that Verilog was not even #2! (Verilog was #3, behind PALASM)
But, you also consider VHDL "a dead language supported only by a few
obscure holdouts in the small-money FPGA world". Interesting, especially
since Synopsys' own FPGA Compiler II is a distant 3rd in the FPGA synthesis
tool market. I guess it is a small-money market for Synopsys. That's what
they call markets where their tools aren't doing very well. I'd bet a few
other vendors would beg to differ on the classification of that market.
I'm sure productivity will increase when the verilog users have access
to the same language features VHDL has had for a decade or more. Just
think where they'd be if they'd used VHDL all along?
- Andy D Jones
Lockheed Martin Moorestown, NJ
---- ---- ---- ---- ---- ---- ----
From: Paul Ramondetta <paul.w.ramondetta=user domain=lmco hot bomb>
John,
I guess Synopsys is following the old GE edict...
If you're not #1 or #2 and you can't fix it, get out of the business!
- Paul Ramondetta
Lockheed Martin Moorestown, NJ
---- ---- ---- ---- ---- ---- ----
From: Dave Chapman <dave_c=user domain=goldmountain wrought balm>
Hi, John,
I saw Aart give the lunch-time talk at the OpenVera Developer's Forum
earlier today. He started by saying that it's not true that VHDL is "like
Latin", and that they would continue to support it for at least 5-10 years.
It definitely sounded like "Goodbye" to VHDL.
One of the slides he put up showed that VHDL goes away in 2003. What caught
my eye was that it also shows Vera, OVA, and PCL going away in 2004.
There were 47 people there (including Sysopsys employees & panelists). Last
year, I counted 89. It doesn't look good for Vera or VHDL.
- Dave Chapman
Goldmountain Consulting Sebastopol, CA
---- ---- ---- ---- ---- ---- ----
From: Jim Evenstad <jevenstad=person company=tsi naught tom>
Mr. Cooley,
I just read your article "VHDL, the new Latin", in the latest EETimes. I am
an FPGA designer and haven't done an ASIC in 20 years. We exclusively use
VHDL and I am responsible for recommending PLD development trends, this is
very important to us. I was disturbed by your article quoting Aart DeGeus
about the demise of VHDL. Was your closing paragraph cynicism or is it what
you believe will happen? Do you see System Verilog taking over FPGA design
or will it stay with ASIC people? If so, what time frame?
- Jim Evenstad
TSI, Inc. St. Paul, MN
---- ---- ---- ---- ---- ---- ----
From: [ A Synopsys Employee ]
Hi John,
It's not absolutely true that Synopsys' R&D group isn't developing any new
VHDL-based tools. They are in-fact developing a *new* Presto VHDL Compiler.
It's no big secret that it is being developed from scratch.
Keep me anon please, if you decide to publish this.
- [ A Synopsys Employee ]
---- ---- ---- ---- ---- ---- ----
Editor's Note: Go to http://www.DeepChip.com/gabe_vhdl.html if you want
to see another more personally humorous story relating to this. - John
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 16,683 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@TheWorld.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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