( ESNUG 443 Item 6 ) -------------------------------------------- [04/15/05]
Subject: ( ESNUG 442 #12 ) Two Users Benchmark DC XG Mode vs. Standard DC
> Overall the process took us about 3 weeks to completely move to DC XG,
> but for the price of a simple top-down compile with an overnight runtime
> for a 500 K instance design, it was well worth the effort. We do clock
> gating with Power Compiler and scan insertion with DFT Compiler. XG is
> not in the Infineon standard flow but with these results we will
> certainly need to consider moving more designs to it.
>
> - Ulrich Zaus
> Infineon Technologies Munich, Germany
From: Marco Brambilla <marco-tpa.brambilla=user domain=st spot gone>
Hello John,
We decided to try out this new DC XG mode with a top down methodology on a
chip that we recently taped out. We used DC 2004.06 leveraging XG's higher
capacity. The final results were interesting:
DC 2003.03 DC 2004.06-SP2 XG Change
---------- ----------------- ------
Area 98 mm2 51 mm2 48% smaller
Runtime 3 Days 22 hours 3X faster
Capacity 16 Gb 9 Gb ~2X smaller
Timing 0 WNS 0 WNS same
To be fair this is not really an apples to apples compassion. With our
tapeout runs we were limited to doing a bottom up compile with minimal
re-optimization due to the amount of time and capacity it took to
synthesize the design. Now with the capacity and runtime improvements
in XG mode we are able to move to a much simpler and optimal top down.
Basically my synthesis script after reading in the code is fundamentally
1 line:
compile -scan
and, had that been available when we synthesized the chip, we could have
saved 2-3 days of work...
- Marco Brambilla
STmicroelectronics San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: Fabio Collina <fabio=user domain=lsil spot gone>
Hi John,
We noticed a significant runtime improvements and memory capacity reduction
Design Compiler, release 2004.12 (XG mode). We monitor DC as part of LSI
Logic qualification regression suite using customer's designs. This test
focuses on runtime and memory request and comprises of a standard top-down
compilation (-scan) based on both Unix and Linux platforms
For two of those designs, based on Linux64 platform, we found:
Test Case 1 (~2 M gates + 107 RAMs)
dc_shell dc_shell-xg
-------- -----------
WNS -0.45 -0.45
TNS -0.83 -0.83
Memory 2.3 G 1.8 G 22% smaller
Compile Time 3.7 hrs 2.6 hrs 1.4x faster
Test Case 2 (~1.5 M gates + 85 RAMs)
WNS -3.01 -2.74 9% less
TNS -1127.39 -429.30 62% less
Memory 3.0 G 2.4 G 20% smaller
RunTime 2.1 hrs 1.4 hrs ~1.5 faster
No changes were needed in the DC scripts, since already tcl-based. Note
that design constraints have been made particularly aggressive in order
to stress DC (runtime).
- Fabio Collina
LSI Logic Agrate Brianza, Italy
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