( ESNUG 475 Item 10 ) ------------------------------------------- [09/18/08]
Subject: The Biggest Lies Told by the EDA Vendors at DAC
OTHER THAN CADENCE: I have to say that I was surprized at how few users felt
they were being tricked or bamboozled at this year's DAC. Other than a few
who felt put out by Cadence not attending, most customers were mostly happy.
"(optional) -- What were the WORST tool[s] or the biggest LIE[s]
you heard at DAC? You can be anon here, but please be specific."
I was disappointed that Cadence skipped this year's DAC. I don't want
their sales people visiting me when I'm just looking.
- [ An Anon Engineer ]
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No Cadence was annoying.
- [ An Anon Engineer ]
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In DAC, I wanted to see the demo of Cadence ADE I/F of FineSim. But I
couldn't do that. No Cadence at DAC.
- [ An Anon Engineer ]
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Biggest lie: Mentor Graphics ADiT. The numbers may look good, but in
practice we haven't seen good results, especially compared to the
competition that their marketing slides clearly were aimed against.
Granted, their numbers were more likely at 90 nm or 130 nm, but many
big players are moving below that.
This is a real pity, as our team has grown to like their mixed-signal
tool (and this from a diehard group of Cadence Spectre users, who were
hell bent on migrating to Cadence's AMS Designer).
Bottom line... I'm still waiting on a vendor to be able to provide all
the working pieces in our AMS flow that we need for our next design.
- [ An Anon Engineer ]
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Avery looked interesting for similar reasons to NuSym, but Avery only
showed slides.
Supposedly, Avery has been working on it for 4+ years... Vaporware?
At least NuSym had some software running.
- [ An Anon Engineer ]
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Synopsys: Parallel VCS - It's vaporware, so why put it on your suite
presentations? Especially when you have to then tell customers that it's
not in a release and the installation is complicated so they'll have
to "work with their AEs to get it".
Synopsys: "System Verilog and VCS" presentation. Misleading title.
This was a complete shill for VMM
- [ An Anon Engineer ]
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Tela Innovations: Not exactly a lie but like 5 years late to be an
"innovation". Take a look at Intel 45 nm silicon or the logic brick
work...
- [ An Anon Engineer ]
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Synopsys - Hierarchical UPF was announced in the Eclypse luncheon. They
have a bottom up flow, but not top down. I double checked that with the
Synopsys expert at the booth. I know this was in their plan for UPF 2.0
version.
- [ An Anon Engineer ]
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Pyxis router as a product is the biggest lie.
- [ An Anon Engineer ]
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Worst product at the show - no competition on this one - Analog Rails.
The demos were far too canned, their pitch was just wrong and not
realistic. They do not understand the concept of release to production
or why a designer would want to work with a fab (that is NOT the same
as having a layout in a canned pad frame on a shuttle run or MPW).
They have no partnerships with any fabs, mask shops or interface to
third party design databases. When asked if they can import - GDSII,
LEF, DEF, OASIS, CDBA ; the response was they did not know what those
format were, they only supported the OA database so they're compatible
with place and route. Their response does not even make sense as
there are no OA P&R tools.
- [ An Anon Engineer ]
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Analog Rails... claims didn't stand up to questions... or perhaps the
tool just isn't ready yet.
- [ An Anon Engineer ]
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Worst tools are all the analog placement tools. Every year we get
several new entrance and none of them ever worked.
- Duc Hoang of Beceem, Inc.
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The biggest vendor lie - "Q: what verification tool runsets do you
support if the design is correct-by-construction? Calibre, Quartz,
Hercules, Assura?" EDA vendor answer - "We do not need those, our
correct-by-construction tool covers all the rules, if you can tell
our AE what the rules should be, they can code the process for you in
under a couple of hours."
The big 4 EDA guys in partnership with the fabs are creating 1200+
design rules for digital, this is not even counting the new application
based and equation based rules, and typically not releasing them more
than 2X per year.
A small company that does not have access to the "undocumented rules
that are runset only" cannot support for anything smaller than 1.0 um
single poly, single tub processes with the knowledge base of the guys
there (no process folks at all, no litho folks at all, no mask layout
people at all). All in all, they are new poster child for "analog
EDA startup bandwagon" from guys who got investment money because it
was the hot train to get on, just as we had our share of "DFM poster
children" who are all gone now, with brightly colored demos, lots of
buzzwords, but no real solutions, and a blight on the EDA community.
Short answer - not good.
- [ An Anon Engineer ]
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OK, this is a little off message but I have to tell you the FUNNIEST
thing I saw at DAC was the Flaming Badger graphic on the Tuscany DA
booth! "No Badgers were injured in the making of this booth." I have
a low resolution snapshot of it if you can tell me how to get it past
your SPAM filter, John.
- [ An Anon EDA Vendor ]
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