( ESNUG 476 Item 6 ) -------------------------------------------- [10/29/08]
Subject: ( ESNUG 475 #8 ) How Apache slowly crushes Cadence VoltageStorm
> At Apache booth, presentations were done by Apache customers. At the end
> of the presentations, I had the opportunity to have informal discussions
> with attendees from other companies about the tool and its day to day
> usage. It was very interesting.
>
> - Remy Chevallier of STmicroelectronics
From: [ Spiderman ]
Hi, John,
Please make me anonymous.
Since you asked, here's my personal thoughts on Apache Redhawk after using
it for 2 years on a variety of chips. We've used it to do:
1. Conventional Static, EM analysis. Far superior than the earlier tools
we were using (VoltageStorm). Superiority is measured in compute
efficiency (speed 5x, memory), handling large designs, people needed
to support the tool and most importantly, the rich analysis and post-
simulation functionalities that ease the silicon debugging. Result:
Redhawk in, replacing VoltageStorm at a fast past.
2. Dynamic voltage drop analysis with Redhawk proved to be a very
significant change in our silicon and power delivery analysis. The
other tool (VoltageStorm-DG) could not compete with Redhawk even
after providing Cadence AE's with the support they need to complete
the task for comparison.
3. Redhawk provide unique capability called "Chip Power Modeling". This
is a compact representation of the die in a form of current waveforms
Icc(t) and impedance Z(f) which can be translated into effective ESC
and ESR (called Cdie/Rdie). This capability is widely used to
support our power delivery design teams.
4. Working closely with Apache, we jointly developed what is called
"Early Analysis" capability. In a nutshell, this capability enabled
us to generate power grid from scratch (based on design specs),
instantiate high level abstract models for the different design
partitions/blocks (current waveforms, caps, etc.) and to then perform
early static or dynamic analysis. This capability is used for the
co-design of the power delivery of our advanced chips and provides
our design teams with more robust power grid to handle the demands
for power saving schemes. With the success of that pilot project,
our other design teams are seeking to do the same for future chips.
We are expanding the early analysis capability to support our chip
architecture team in order to estimate performance and optimize
design specs (budgeting, etc).
5. Also we worked closely with Apache to develop the extraction and
circuit reduction of a power grid to support the spice-like analysis
of sensitive analog blocks like DDRx, FSB, LVDS, PCI-E, etc. At the
beginning we thought that this to be a small feature in Redhawk, but
it ended up to be a very critical capability that was requested by
several of our projects. It has been used successfully to quantify
jitter, coupling and to save significant effort of re-designing the
power delivery network in order to meet specs in time. It enables
extraction and reduction of R, RC and RLC power grid. We validated
the accuracy of the R reduction to be extremely accurate (within under
0.1% from the unreduced netlist while the reduction is from millions
of components to tens or hundreds or few thousands depending on the
number of ports. E.g. Reduced ~1.7 millions DDR3 VCC power grid to
under 400 components for 28 ports netlist and the maximum difference
in any effective port-2-port resistance under 0.1%.)
6. Redhawk can perform dynamic based clock and critical path analysis.
It was very useful to study the impact of the dynamic voltage drop on
our clock jitter, timing and even functional failure prevention.
7. We were able to integrate our internal modeling and circuit simulators
for cell-based and custom IO characterization for Apache Redhawk use.
8. We just started to use (evaluate) the Redhawk capability called "TOTEM"
for custom IO and SRAM analysis (earlier we had used Redhawk-MMX). It
seems to be a big jump to ease the modeling and analysis of the custom
circuits. Analysis is at the block/partition levels as well as at the
fullchip levels.
9. Redhawk can optimize our explicit Decaps, consider the trade-off
between power, leakage and die area. In addition, it can fix the power
grid. This combination is a very potent feature to reduce the number
of design cycles.
10. Redhawk also has dynamic based SCAN and Memory BIST analysis modes. It
has been found to identify serious yield issues and to mitigate and
eliminate those worst case SCAN and Memory BIST testing issues.
11. There are other capabilities in Redhawk which we looked at but we did
not get the chance to utilize it yet. These capabilities are:
- Thermal and thermal-electrical analysis (called Sahara)
- SIP and true Die-Package co-design (after the merger of
Optimal with Apache)
We are convinced that these capabilities are very important, but we did
not get the chance to utilize it due to bandwidth and resources.
I should mention that working with Apache AEs and R&D is unmatched with
all the other EDA vendors. Definitely there is no comparison with Cadence,
Synopsys, Mentor, nor Magma. I found dealing with Apache personnel at
different levels (AEs, R&D, Marketing, and management) is as the difference
between A and C grades.
By the way, I surveyed almost all the available capabilities in the industry
(not just a few). What struck me is to find that ONLY Apache management and
staff are compassionate and dedicated to provide the best "Power Integrity"
solution (money comes later) while others were doing a "me, too" catch up or
just maintaining their outdated solution and just trying to milk it as long
as they can taking advantage of some business alliances where customers may
be obliged to buy from them just because they have a corporate deal (!!!)
- [ Spiderman ]
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