( ESNUG 540 Item 2 ) -------------------------------------------- [05/16/14]
Subject: Hogan on how ultra low voltage design changes energy and power
From: [ Jim Hogan of Vista Ventures ]
Hi, John,
In an energy-constrained world, design is a series of trade-offs to balance
between minimizing energy for a given performance requirement and maximizing
performance for a given energy budget.
Many designs need maximum throughput with little latency. There's nothing
that can be done to cut their energy use.
But many other designs can either tolerate a large latency or just requires
some minimal perceivable throughput. For these designs, their excess
performance from a given architecture can be traded for energy savings.
Let's look at present-day chip energy usage for:
1. Smartphones. An iPhone5 consumes 1,440 mAh per battery charging.
Given typical usage, it requires a recharge every day. Today's
smartphone chips already have aggressive voltage-scaling for
power management already built-in.
2. Implanted medical devices. Pacemakers, neural stimulators,
cochlear implants consume ~5-10 uA. And ~30% of this is required
for heart stimulation, so that part cannot easily be reduced.
However, sensor-only implants can be much lower power.
Battery-based systems require intrusive replacement every 5-8
years. Inductive recharging was used in early stages, but was
too vulnerable to human error; people would forget to recharge,
hence the maker was exposed to litigation. Plus inductive
recharging has a noticeably shorter service life than modern
non-rechargeable lithium Iodide batteries.
Many of the energy-saving techniques in this area are focused on
analog sections -- potentially operating near-threshold -- though
digital sections also benefit from "traditional" voltage scaling.
3. Base-stations. Some estimates put the total Verizon utility bill
at $1 billion a year. In the race to provide the greatest cell
tower coverage, this is an important cost to control.
4. Regulatory pressures. Energy efficient Ethernet, driven by the
EnergyStar initiative, aims to reduce power during low-link
utilization.
5. Low power servers. Facebook approached 700 Giga W-hr in 2012.
Modern server-class processors consume ~100 W when running at
full speed. New ARM-based entrants are more in the 20 W range,
matched now by Intel's latest Xeon E3 offerings. Reducing
data-center running costs is a big driver.
These are all areas where a lower power chip have a global impact on world
energy consumption.
---- ---- ---- ---- ---- ---- ----
WHAT CAN WE DO IN DESIGN?
Last year I had the good fortune to attend a lecture by Jan M. Rabbaey on
Low Power Design Essentials. He did an excellent job of mapping several of
strategies for lower energy with design.
He explained what he called the "Design Abstraction Stack". Higher you go
up the stack, the greater the energy cutting ROI.
Abstraction
Level |
Actions |
ROI |
| Algorithmic |
selection of chip algorithms |
orders of mangnitude,
10x to 1,000,000x |
| Behavioral |
amount of concurrency,
memory use |
several times,
2x to 9x |
| Power Management |
clock control |
10% to 90% |
| RTL |
structural transformations |
10% to 15% |
| Technology Independence |
extraction and decomposition |
15% |
| Technology Dependence |
mapping,
gate sizing |
20%
20% |
| Layout |
placement and routing |
20% |
Traditional energy reduction techniques include scaling of fab processes,
reducing supply voltage, and eliminating waste.
Then he covered options in relation to their abstraction layer.
System/Application - choice of algorithms
Software - amount of concurrency
memory use
Micro-architecture - parallel vs. pipelined
general purpose vs. application specific
Logic/RTL - logic family
std cell vs. custom
HDL coding styles
Circuit - sizing
voltage supply
thresholds
Device - bulk CMOS vs SOI
In this ESNUG post I wish to examine how the recent trend of dropping the
on-chip voltage (VDD) -- to cut power -- ripples throughout every stage
of chip design. Simply put:
Power == (Voltage^2) / Resistance
That is, as a chip's VDD drops linearly, power use drops geometrically.
This is why from 2006 to 2016 (est) as it's gone from 65 nm down to 10 nm,
Samsung has also reduced it's Vdd supply voltage from 1.2 volts down to
(a planned) 0.7 volts.
What follows are the nuances of how dropping to ultra-low voltages (to
save on power, and while still maintaining performance over a range of
temperatures) impacts how our chips are designed.
- Jim Hogan
Vista Ventures, LLC Los Gatos, CA
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