( ESNUG 545 Item 4 ) -------------------------------------------- [12/12/14]
From: [ Trent McConaghy of Solido Design ]
Subject: Solido Brainiac Trent's Trip Report on CICC'14 in San Jose, CA
Hi, John,
The 2014 Custom Integrated Circuits Conference (CICC'14) was held in the
Doubletree San Jose from September 15-17, 2014. There were 283 attendees.
This report covers some of the talks I found particularly interesting.
- Trent McConaghy, CTO
Solido Design Automation Saskatoon, Canada
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CICC Keynote: Dr. Ahmad Bahai, Texas Instruments
Dr. Bahai reviewed many of the major trends in the semiconductor world.
Perhaps most notable is the trend in cost of silicon. A decade ago, you
could get 2M transistors for $1. Each year reduced the cost exponentially;
now you can get 20M transistors for $1. (7G devices for $350) But... it's
not only flattened, it's trending downwards: the next process node will
actually only buy 19M transistors for $1!
Dr. Bahai spent much of his talk discussing power management. A modern
data center (e.g. for Google) occupies 43,600 square feet (10 football
fields), has 100K servers, and uses 48MW. Wireless data infrastructure is
computed to need 30 TWh. Naturally, this increases demand for improved
power management infrastructure. Direct conversion using solid state
transformers promises 10x better power density. Dr. Bahai gave several
examples where ideas from signal path engineering are being ported to power
management.
Dr. Bahai also described how, because SOCs have been optimized so well for
power, packaging is becoming the larger contributor to power loss. SIP
(system in package) is becoming critical; and flip-chip is more promising
than TSV.
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Paper: Technology-Design-Manufacturing Co-Optimization for
Advanced Mobile SOCs
Author: Dr. Geoffrey Yeap, Qualcomm
In 2011, the installed base of smartphones surpassed PCs. That makes mobile
the leading computing platform. In 2012, there were approximately two
smartphones shipped for every PC. In 2013, there were 1.013G smartphones +
tablets shipped; this is predicted to rise to 1.734G for 2017, with most of
the growth in up-and-coming economies like China and India.
In the semiconductor market, cellphones are $64.3G, with a 15% CAGR.
A modern mobile SOC has a huge amount of functionality: CPU, GPU, memory,
RF, power management, modem, connectivity, GPS, multimedia, DSP. What's new
is a "natural language processor" and a "contextual computing processor".
Basically, any popular functionality that sucks power is getting frozen into
silicon.
Mobile data traffic is on the rise. In 2012, a typical smartphone user
used 50x more data than a feature phone. An LTE user used 2.3x more data
than a 3G user. Experts predict a 1000x data traffic increase by 2020.
Dr. Yeap called this the "1000x mobile data challenge".
28nm was the first node where mobile computing was driving semiconductors,
in the sense that mobile computing chips were the first to ramp to volume.
Before that node, computing was the driver.
In alignment with the keynote speaker, Dr. Yeap said "continued Moore
scaling is threatened by economic challenges", and specifically "20nm will
never be cheaper than 28nm PolySi".
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Paper: Challenges of Analog Circuits on Nanoscale Technologies
Author: Dr. Greg Taylor, Intel Circuit Research Lab
Here are some takeaways:
- Intel's 1992 processors had two analog blocks: a PLL and
an I/O. Now, there are >30. Each processor generation
on average has four new unique analog blocks, improves
performance 50%, and analog takes 2% more die area.
- Analog is interesting and challenging because of noise
and random variation. Regarding noise, thermal noise is
less of an issue but the 1/f noise gets worse every
generation, which in turn reduces dynamic range in every
generation. Regarding random variation: by Intel's
measure the standard deviation of threshold voltage
variation was 25 mV in 130nm, 35 mV in 90nm, 38 mV in
65nm, and 45mV at 45nm.
Dr. Taylor reviewed a variety of design techniques used at Intel to manage
variation.
- First is simply increasing the circuit sizes -- what he called
"brute force".
- To improve upon that, in many cases one could have five devices
side-by-side and pick the one closest to nominal -- what he called
"redundancy". There are fancier redundancy variants such as
picking the 6/10 closest to nominal. Unsurprisingly, redundancy
sacrifices much less area than brute force for the same reductions
in yield loss. For example, brute force needs 256x more area to
go from 10% to 1% yield loss, and redundancy needed only 1/10th
that amount.
- Another related technique was to put 256 identical components in
parallel and pick the best 128, such that "variation is a feature,
not a bug" (Ref. Daly, ISSCC, 2008).
- Another family of approaches is "synchronous techniques" like
offset zeroing in amplifiers.
- Another technique is to average out variation in the time domain,
such as dynamic element matching.
Dr. Taylor also discussed statistical tools:
- "Increasing device variation requires variation-aware design".
- This is not to be confused with worst-case design, which is too
pessimistic to be practical. Also, one cannot simply apply "skew"
corners (e.g. FF) because that does not highlight the impact of
within-die variation.
- Rather, one must use statistical techniques to help predict and
understand variation. He discussed Monte Carlo and Design of
Experiments (DOE) as essential tools, with the caveat that "these
tools don't replace the need for engineers to understand
statistics".
- Dr. Taylor also stressed the importance of "validation", i.e.
verification at the tail end of the design process. In this step,
Greg included circuit simulation as "necessary but not sufficient".
He also included mixed-signal validation leveraging RTL simulation,
and design reviews.
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Paper: Uncertainty Quantification Techniques (ie Variation-Aware
Techniques) for Electronics Systems
Author: Dr. Luca Daniel, MIT
Dr. Daniel and his students Zheng Zhang and Tarak El Moselhy have been
working on technology for problems like yield estimation and variation-aware
parasitic extraction. But the technology itself is extremely general, not
limited to circuits.
Dr. Daniel showed a general way to describe these problems (including
recent advances in this understanding), a set of steps address the defined
problem, and benchmark results. I believe this is an extremely important
body of work for circuits and for engineering in general, so I'll describe
it in detail.
The problem is defined as: given some statistical representation of
parameter variations, and an operator (e.g. differential algebraic
equations / DAEs for circuit simulation or ordinary differential equations /
ODEs for parasitic extraction), then generate some statistical
representation for the output.
There are several possible statistical representations for the output:
probability density function (PDF), statistical moments, surrogate models,
and the samples themselves.
To get to the representation in the first place, one starts with the system
to be analyzed. This is either a physical prototype, that you take
measurements from and thereby become samples. Or, it is a model with DAEs /
ODEs (e.g. describing a circuit's transistor dynamics) along with the
statistics of the random variables (e.g. device-level local + global
variation). From this model one can get to a samples representation (e.g.
Monte Carlo sampling + SPICE simulation), or to a surrogate model
representation using "intrusive solvers".
One can transform *among* the statistical representations with appropriate
operators. For example, to go from samples to a PDF one might use density
estimation (e.g. kernel density estimation); and to go from a PDF to
samples one uses Monte Carlo sampling. To go from a PDF to moments one uses
analytical or quadrature methods. To go from samples to moments one uses
quadrature or Monte Carlo. To go from surrogate model (e.g. quadratic) to
moments, one uses APEX (Li et al, IEEE TCAD, 2004). To go from model to
samples one uses Monte Carlo, and to go from samples to model one uses
model-building (e.g. least-squares fit on a quadratic template).
Different statistical representations are useful for different analysis
goals. For example, with a PDF one might estimate yield or do pricing via
binning. Or with surrogate models one might address an inverse problem.
One of the big advances within Dr. Daniel's group is the development of
"intrusive solvers" to go from a model with DAEs / ODEs + statistics of the
random variables, to a surrogate model representation. Dr. Daniel gave a
general framework for Intrusive Solvers:
1. Represent the solution as a generalized polynomial chaos
expansion. (Polynomial chaos is less fancy than it sounds: it's
basically polynomials that are orthogonal to the PDF; nonetheless
given its usefulness it is under-appreciated. "Generalized" in
this context simply means supporting non-Gaussian PDFs.)
2. Substitute the polynomial chaos solution into the DAE/ODE
equations of the problem. This defines a "residue".
3. Force to zero the projection of the residue on a subspace of
"testing" functions. One approach is the "Stochastic Galerkin"
method (aka Stochastic FEM), where the testing functions are
Galerkin functions (orthogonal to the same basis functions as
solutions) . Another approach is "Stochastic testing" where the
testing functions are collocation (ref. Zhang et al, IEEE TCAD,
October 2013). This approach handles strong nonlinearities yet
only needing one sample for each polynomial coefficient (a small
number).
4. Solve the resulting system of equations for the polynomial
coefficients (the parameters of the polynomial chaos model).
Dr. Daniel described benchmarkings of Monte Carlo versus Intrusive Solvers
to a few statistical estimation problems.
- In a DC circuit: Monte Carlo took 493 s, Stochastic Galerkin took
1.1 s, and Stochastic testing took 0.3 s.
- In a transient problem, Monte Carlo took >1 day, whereas
Stochastic testing took 21 s.
- In measuring periodic steady state of an oscillator, Stochastic
testing was 500x faster than Monte Carlo.
Dr. Daniel's group developed a couple techniques to handle >100 parameters:
either constructively build up from low-dimensional subspaces, or exploiting
the sparsity of the hierarchical structure of parameters.
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Paper: PPV-based modeling and event-driven simulation of
injection-locked oscillators (ILOs) in System Verilog
Author: Jaeha Kim, Seoul National University
PPV stands for perturbation projection vector.
Dr. Kim and his students have been leveraging PPV technology as part of
their ongoing work on XMODEL, a new type of simulator targeting fast
simulation of AMS systems. Whereas SPICE transient simulation models a
signal as a series of points and computes it one time step at a time, XMODEL
is event-driven and has no dependence on time steps.
Instead, it expresses signals in a functional form, and events occur when
the functional form's coefficients are updated. XMODEL's functional form
can accurately express a wide variety of signals, such as sinusoids, ramps,
steps, etc. It has a straightforward s-domain representation, which makes
it easy to apply frequency-based operations like lowpass filtering, in a
completely algebraic fashion. XMODEL "netlists" are simulated by
SystemVerilog.
In previous works, Dr. Kim and his students have showed simulation speedups
of AMS systems of 100x and more. This shouldn't be surprising, given the
natural advantages of XMODEL over SPICE representation in AMS-style
scenarios. But there was a limitation: in any AMS circuits which have
injection-locked oscillators (ILOs), XMODEL didn't have a straightforward
way to handle them. Therefore SPICE would be needed to analyze the whole
circuit, losing the 100x+ speedup opportunity. This paper at CICC changed
that, showing how to extend to ILOs. The approach taken was a nonlinear
piecewise ODE, solved by decomposing into a Volterra series.
The approach was demonstrated on an LC oscillator. Dr. Kim showed how
XMODEL had the same accuracy as Cadence Spectre, where Spectre took 5.73 s
and XMODEL 2.02 s. Of course, the real gains come when simulating the whole
AMS system and the LC oscillator is just one block.
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Paper: Efficient Per-Element Distortion Contribution
Analysis via Harmonic Balance Adjoints
Authors: Bichen Wu and Jaijeet Roychowdhury, UC Berkeley
The problem of per-element distortion analysis is to identify the relative
impact of each device with respect to distortion. This information can be
used by designers to make changes to specific devices to reduce distortion.
"Distortion contribution of a device" was defined as the difference between
the distortion response of a nonlinear device, compared to its linearized
version. The challenges are (a) how to linearize the devices individually,
and (b) how to solve the harmonic balance equations to compute the output
distortion. This can be done in a brute force fashion, taking N+1
simulations where N is the number of devices. Bichen Wu described how to do
this much more efficiently by using harmonic balance adjoint sensitivity
analysis -- basically approximating distortion computation with
cheap-to-compute derivatives. This isn't as accurate in an absolute sense,
but it is accurate enough in a relative sense and therefore preserves the
ranking of distortion per device. On a differential pair, the proposed
approach was about 4x faster, with the same ranking accuracy. On a 741
opamp, the proposed approach was about 10x faster.
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Lunch Keynote: The Troubled Birth of Electrical Engineering
Lessons Learned from the First Transatlantic
Telegraph Cable
Speaker: Dr. Tom Lee, Stanford University
It was amazing to hear about the efforts to try to transmit data 3000 km
*without amplifiers* in the mid 1800s.
The first several tries were extreme failures, largely because the project
leaders did not understand the importance of science, and chose the wrong
advice. One advisor having no scientific training (Morse) said to use
small-diameter cables, and another advisor *with* training (Lord Kelvin)
said to use large cables. The leaders chose the small-diameter cables
because it was more convenient... and failed. In the follow-up inquiry, it
became apparent that the language to talk about the failures didn't even
exist. This spurred development of concepts like voltage, current, and
resistance.
The backers gave the project one more chance, with the constraint that Lord
Kelvin lead the technical side. He led it, the project succeeded, and ever
since then Europe has been connected to Canada (and that other country).
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I hope your readers found these conference highlights useful.
- Trent McConaghy
Solido Design Automation Saskatoon, Canada
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