( DAC 01 Item 31 ) --------------------------------------------- [ 7/31/01 ]
Subject: Plato, Avanti, Cadence 'Silicon Ensemble', Synopsys Route66, Magma
TERROR SHOPPING: With half the P&R world's users worried that they're about
to lose their Avanti tools, Apollo users at this year's DAC were frantically
seeking alternatives to Apollo *and* Silicon Ensemble. Yup. That's right.
I said alternatives to Silicon Ensemble, too. Why? Because the original
reason why they bought Avanti despite the ugly lawsuits & accusations was
because Apollo consistently benchmarked better than SE. And if *you* were
about to lose your first class Avanti P&R tools, would *you* want to go back
to their second place Cadence equivalents?
Beyond the recent developments in the Avanti/Cadence lawsuit, more bad news
has plagued Avanti users. Yea, Synopsys has its new Route66 router, but it's
green software that needs debugging. SVR used to be pretty big before Avanti
came around, but SVR has always been poor substitute for Apollo. The only
other alternative is Plato's NanoRoute. From the customer benchmarks I've
found, Plato seems to be doing pretty well, but it's just a router and NOT a
replacement for all the sweet things a complete suite of Avanti tools can do.
Magma is supposed to have some good P&R stuff, but it's still beta code and
it's wrapped up in their BlastFusion toolset. And so far, nobody's confirmed
even one Monterey tape-out -- so they're even more buggy than Magma/Route66.
All in all, there just aren't that many truely viable substitutes for a
complete suite of Avanti tools on the market these days.
"What torques me off is that Avanti and Cadence are actively working
to make their tools NOT work with others."
- Michael Fliesler, AMD
"My observation was that Avanti does not actively support 'standard'
design formats like LEF/DEF or PDEF."
- Dale Lomelino, Philips Semiconductors (ESNUG 373 #4)
"I was at my customer's site last week to debug a DEF in/out problem
between PhysOpt and Cadence SE. It appears that in the latest version
of SE, there is no longer an option to output DEF 5.2; only DEF 4.9
and DEF 5.3 were listed as supported. The problem, of course, is that
DEF 5.3 contains numerous syntax cases not in DEF 5.2 that cause
Synopsys def2pdef to fail. Some of these are: VPIN, SUBNET, CLOCKROOT,
+ USE CLOCK, + ORIGINAL.
It appears to be a deliberate attempt by Cadence to break the interface
between PhysOpt and SE. I can't say I blame them for trying."
- from "Elf Boy" in ESNUG 370 #2
"Synopsys:
Announced a std-cell router, based on Everest/Gambit technology. I
heard that they were still looking to buy such a router six months
ago. Their confidence in the router seems weak, if this is true.
Competitors point out that Chip Architect, Arcadia, and FlexRoute have
not done well. Anyway, the router is called Route Compiler, in an
attempt to hang on to Design Compiler coattails. One interesting
idea is to detail route long nets after the short ones. The rationale
is that detouring short nets from their global routes causes more
timing problems than long ones."
- Deepak Sherlekar of In-Chip Systems
"Synopsys ClockTree Compiler:
Their CTS tool, now in limited partner release, is built into PhysOpt.
This allows it to shift cells to place clock buffers. They claim
competitive QOR, stating 5-20% better insertion delay and 5-10% better
clock skew using ClockTree Compiler/Route Compiler/Arcadia than a
baseline flow using Cadence/Avanti CTS/route/extraction. It uses a
true global route to make decisions, and the global route is kept for
the detailed route. It supports gated clocks, stop pins, & dont_touch
pins. I asked about useful skew. That might be down the road a bit.
Route66 (Route Compiler):
Route66 is built into PhysOpt. It has built in 2.5D extraction, runs
on multiple CPUs and includes a comprehensive layout editing
environment to edit global route, detail route, & GDSII data. Route66
includes Signal Intregrity prevention and repair using the PrimeTime-SI
engine. Their differentiation lies in the detailed routing of local
nets during the long net planning stage. (This is supposed to minimize
local hot spots and produce more predictable long net routing.) The
Synopsys droids claim it reduced total wire length and an average of 5%
improvement in via count."
- Bob Wiegand of NxtWave Communications
"This DAC Synopsys announced Route Compiler (Route66) and clock tree
synthesis. These tools are in beta now, will be in "limited partner
release" in Q3, but won't be released until mid-2002. They're not
committed support for Linux, but 'they're considering it'."
- Kris Monsen of Mobilygen Corp.
"Route66:
This is the much publicized product from Synopsys. It is a standard
cell router. This product is currently in beta testing with some of
their large customers. Route66 will be available on a limited basis
in Q4,2001 and for general use in Q1, 2002. The demo design was a
5 Kgate, 100 MHz design in 0.18m. Key Route66 features:
* Emphasis on signal integrity and timing. Early prevention using
gate sizing and buffer insertion, analysis using PrimeTime-SI,
and repair.
* Multithreading - without multi threading, they claim run times
comparable to Avanti Apollo II. With multi-threading these run
times are significantly improved.
* Built-in chip finishing capabilities. (metal slotting, fill, diode
insertion)
* Very innovative global routing capabilities. However, this global
router is not integrated with their PhysOpt yet!!! They expect
to complete the integration later this year.
* ECO routing capabilities.
* Antenna avoidance (either through modifying the routes or through
diode insertion)
* Ease of use. This is emphasized through out all of the demos.
Route66 can be invoked from the PhysOpt GUI.
* Route66 is timing aware. Once again, it was not clear whether this
timer is the same as that in PhysOpt and PrimeTime.
Route66 does not offer any post route timing/crosstalk optimization
capabilities such as gate sizing and buffer insertion. According to
Synopsys, the design is timing clean once it comes out of PhysOpt. ECO
capabilities may be limited. It also looks like Route66 is limited in
its connectivity driven editing capabilities. It looks like it has
complete DRC checking capabilities."
- [ An Anon Engineer ]
"I looked at Synopsys's Route Compiler and the Clock Tree tools. The
router looked pretty, but they had little competitive results data.
I would like to see it in action. I was disappointed in the amount of
info that was given on the clock tree tool for PhysOpt. It seemed to
me to be only briefly covered. I wanted real results data on skews of
large designs."
- Phil Kuglin, Credence Systems Corp.
"Interested in what Synopsys has to offer, Route66. Too soon to tell.
Avanti suit has put FUD back into the equation. Trying to predict
what a court will decide is well... they let O.J. go free so you go
figure? We have a significant investment in Avanti tools. At the
technical level we feel Avanti has a superior product to Cadence. I
am aprehensive to make any more significant investments before the
smoke clears on this recent round of court room adventures however,
so it is wait and see for the moment."
- Phil Hoppes, Intersil
"Avanti: I haven't used it. It has a reputation for being somewhat
better than Cadence SE.
Cadence Silicon Ensemble (or whatever they have renamed it to this
year): It's what we use here for block routing (routing inside
place/route and datapath blocks). We use it because it's a safe,
known quantity.
Synopsys Route66 Compiler:
Gambit was purchased by Synopsys, and is the basis for Route66 (now
Route Compiler.) It is very powerful, and very programmable/tunable,
and can probably route things that no one else can. The downside was
that you tended to need a team of Russian PhDs to keep it working. I'd
like to send them a test case, but they're only working with existing
PhysOpt customers for now. It will be interesting to see what whether
they've been able to turn it into a stable product without taking away
too much of the power and flexibility.
Plato:
We'll see how they do on the next test case. I'm a bit worried that
they're working on new stuff like the optimizer, at the expense of the
router.
Synopsys FlexRoute:
Much faster than the other main gridless router out there (Cadence's
IC Craftsman). We have used both here, and replaced IC Craftsman with
Everest, which became FlexRoute. We also use it for top-level
floorplan management and pin assignment. One nice feature is that it
can be driven by a Perl API, very refreshing after seeing so many TCL
driven tools. It has been somewhat buggy, has had a tendency to change
features from one release to the next. Stability is getting better,
but is not up to par with other Synopsys tools.
What's my motivation for looking at new routers? I'd like to be able
to buy an un-bundled router so I don't have to buy all of the baggage
from Cadence or Avanti every time I want to add routing capacity."
- [ An Anon Engineer ]
Synopsys' announcement of Clock Tree Compiler was nothing short of
disappointing. There had been some talk several months ago about a
clock tree synthesis tool from Synopsys that would use clock skew to
fix timing. When they announced yet another zero-skew clock solution,
I again remembered why I wasn't in marketing.
- Mike Berry, Silicon Logic Engineering, Inc.
"Of the announced new router tools, Plato's NanoRoute is much more
interesting than Synopsys' Route Compiler (Route66). At DAC, Synopsys
was relying heavily on FUD to make their router attractive. Plato is
pushing results."
- Mike Carter of Mosaid Technologies
"Plato/NanoRoute
New company, demo'ing a router that can be used for both blocks and
top-level claim 10x faster than traditional Cadence/Avanti routers 2-3X
faster on single-cpu machines 3-4X faster running on a 4-cpu machine,
able to parallelize routing job router is neither grid-based nor
shape-based, something in-between, closer to grid-based. Benchmark
quotes, for a 505 kgate placeable instance, 501k net design:
63 minutes to completion on a 10 CPU machine
7 hours on a single CPU machine
More oriented towards Cadence flow, currently; reads LEF/DEF/SDC/.lib;
They're working on Avanti flow now (bad for us). They're able to
apply signal integrity constraints (coupling cap limits, parallel
length limit), available Q3'01, overhead of 30% extra CPU, 5% extra
memory able to do repeater insertion, upsizing/downsizing, incremental
placement can taper clock nets, does not do shielding today comes with
GDS viewer, but no editor (so not so good for handling unrouted nets.)
Nice GUI, quick refresh, one tapeout today, 3 on the way, hungry..."
- [ An Anon Engineer ]
"My eval found Plato routing speed much faster than Apollo. If I use 4
CPU, the routing speed is almost 8 times Avanti. My test design stats:
Number of Macro Cells: 36
Number of Module Cells: 402,309
Number of IO Pins: 4,014
Number of Nets: 241,776
Average Pins Per Net (Signal): 3.11189
Chip Utilization:
Total Macro Cell Area: 955,792.81
Total Standard Cell Area: 7,611,946.94
Cell/Core Ratio: 97.5404%
Number of Cell Rows: 681
Core Size: width 2303.28, height 3813.60; area 8783788.61
Chip Size: width 2304.40, height 3824.80; area 8813869.12
Apollo took 8 hours. Plato NanoRoute took 55 minutes. In general, we
like NanoRoute very much, particully the scalable routing speed."
- [ An Anon Engineer ]
"I think that truely "parallel" tools like Plato's NanoRoute are needed
to achieve high throughput and meet tight deadlines. You still need to
use "Qplace" or another placement method (InternetCAD.com?), but this
router rips. I mean it's fast..."
- Tom Moxon of Moxon Design
"We ran Plato NanoRoute on an 8-CPU machine (480Mhz) on a 200 K
instance block in less than 1 hour. We are using NanoRoute for
tape-out now."
- Charlie Ma, Ciena Corp.
"Our benchmark results briefly (design with 353 K instances):
Runtime Initial Routing Viol
Plato 4 h 0
Cadence 35 h 330
Avanti 42 h 13,000
In this benchmark Plato used a 4 processor machine, built in RC
extraction and timing calc + STA."
- [ An Anon Engineer ]
"What Plato showed at DAC is still in alpha phase and will take sometime
for NanoRoute to be production worthy. I am mostly interested in
getting a router which has very high capacity & can do noise avoidance
or optimization during routing. I haven't found any tool which has
even attempted to do what Plato is claiming they can do. I already am
using the FixIt (new tool) from Sapphire which does in-place fixing for
timing and noise based on routed-SPF from Apollo. It seems to be doing
a decent job. We still are struggling with the Apollo router capacity
and runtime problems.
I have used most of the tools in the industry and I think Warp router
is the best router (without noise optimization) in the market to date,
but all the other Cadence tools suck. Apollo router is in the final
dying phase as far as I am concerned. SPC claims that they will have
the Beta version of a router sometime later this year."
- [ An Anon Engineer ]
"Plato NanoRoute vs. Avanti Apollo Benchmark
-------------------------------------------
Design of 706,601 Cell Instances, 326 I/O, 37 Memory Instances
2 Custom Macros, 747552 Nets, TSMC 0.18
Peak Memory Run time # DRC # antenna
OS/ # CPUs # CPU used used - Mb Hrs:min viol. viol.
----------- ------------ --------- ------- ----- -----
Sun Solaris Apollo 1 6.84 36:00 0 N/A
2 x 750 Mhz NanoRoute 1 1.32 10:12 0 N/A
NanoRoute 2 1.34 7:10 0 N/A
Sun Solaris
4 x 480 Mhz NanoRoute 2 1.34 8:19 0 N/A
PC Linux
2 x 933 Mhz NanoRoute 1 1.33 10:00 0 N/A
PC Linux NanoRoute 1 1.28 7:49 0 N/A
2 x 1 Ghz NanoRoute 2 1.34 6:00 0 N/A
NanoRoute 2 1.55 7:25 0 0
I was so impressed with these results I immediately started using Plato
in our production flow for this design.
The beauty of this tool is it uses standard LEF/DEF I/O and Tcl for
it's interface. No training required to use this tool. Download it,
untar it, brief through a few pages of very consise, easy to read
documentation using your favorite web browser and you're up & running.
It has a simple user interface and it is very easy to learn and use.
I was routing my design within an hour of downloading the code.
One thing you can't do with NanoRoute is power route or assemble your
physical design. I wasn't to excited about having to purchase Apollo
or SE for power routing and chip assembly so I started looking for
alternatives. I found Stabie-Soft www.stabie-soft.com offers a chip
assembler, floor-planner, power router, layout editor that has proven
to be very effective and inexpensive.
Since my benchmark, our design has gotten more complex. The current
version is running in 9 hours and 2 minutes resulting in 0 DRC and 0
antenna violations using 1.6 GB of memory on a $4,000.00 Linux box.
My benchmark suggests Apollo would run this design in 44.8 hours
without antenna fixing on a $40,000.00 SUN 750. I'm impressed."
- [ An Anon Engineer ]
"Plato's performance and quality are real. The problem with Plato is
even if you like their NanoRouter, you have to buy it in addition to
your existing Cadence or Avant tool set. That makes them only
suitable for the high-end customers who has a deep pocket and will
pay for productivity gain at any cost. As for me, I'll make sure that
my Silicon Ensemble license are optimally used 24 hours a day."
- [ An Anon Engineer ]
"But the most impressive about NanoRoute is the quality of routing. I
was able to route DRC clean on 6 designs which the routers from big
guys left with DRC violations. Here's my stats on another design:
Network Application Chip (0.18u, 125MHz)
NanoRoute Cadence Wroute Apollo
--------- -------------- ------
Elapsed time on E4500: 3:57:19 24:19:57 28:57:43
Remaining violations: 0 330 3,042
Three of the designs only Nanoroute could finish without shorts. The
pin to pin routing saved days of manual work for a straight routing in
the I/O area. The timing is better on all 6 designs. In one design
NanoRoute reduced timing down from 354 timing violations to 70. It's
layer by layer congestion map in the GUI gave the final understanding
of congestion caused by the bad Floorplan. This is the fastest GUI
ever saw can show the routing."
- [ An Anon Engineer ]
"I attended the demo of NanoRoute by Plato. To my understanding it is
a new approach ("graph based routing") anywhere in between grid-based
routers as Apollo and Astro by Avanti, and shape-based routers as
Dolphin by Monterey with advantages of each algorithm. Plato reads in
LEF and streams out LEF. Therefore the user has to perform DRC/LVS
on LEF format which - to my opinion - causes additional work if an
existing design environment is available and NanoRoute is to be
integrated, i.e. performing DRC/LVS on GDSII. To Plato's credit, this
"flaw" will be changed with next release in September. I think that
this tool becomes very important if the "flaws" have been fixed. But I
also see that the company might be taken over by any of the big ones
because the staff is relatively small (~ 15 people).
Route66 Compiler is - to my opinion - an advanced tool which offers
features other tools don't, e.g. "island style metal slotting of fat
wires". This is solved by post processing & LAPO runs."
- [ An Anon Engineer ]
"Avanti
------
I wasn't able to spend much time looking at Avanti's tools. Their
tools don't seem to offer a coherent, single-pass design flow. Of
course, they offer many popular back-end tools we should look into:
1. Jupiter: a design planning & physical synthesis tool
2. Planet-PL: floorplanning, front-end to other tools
3. Apollo II: a popular router
4. Saturn: an optimization tool that works with Apollo-II to do
buffering, cell resizing (IPO), logic restructuring & duplication,
etc., some of this post-route.
5. Hercules II: a popular DRC/LVS tool
Seems like a lot of the features of these individual point tools are
provided in a more integrated, simultaneously-optimized fashion in
offerings from other vendors.
They only advertize support for Sun Solaris and HP-UX."
- Kris Monsen of Mobilygen Corp.
"We are committed to Avanti. Hope the lawsuit works itself out. Might
be interested in testing out the Synopsys tools if they when get an
integrated database and tie them all together like Avanti. Until then,
no point."
- [ An Anon Engineer ]
"I have to admit that Avanti's legal woes have considerable weight
on my shopping trip."
- [ An Anon Engineer ]
"Avanti Astro:
This is the next generation place and route product from Avanti. The
demo design is a 2 kgate, 0.18 um design at 300 MHz. Key features:
* New Milkyway database that has shared memory capabilities
* localized parasitic extraction capabilities (making the pre-route
RC extraction very accurate)
* New netlist optimization capabilities -
Preplace - synthesis of the netlist based on the physical parameters
Inplace - during placement, Astro will optimize the netlist and even
build clock trees on high fanout nets (this is a feature
that was not present in the competitor's products)
Postplace - optimization after placement
* new clock tree synthesizer (this is completely re-written and will be
enhanced to take the useful skew features into consideration)
* new timer with enhanced schematic probing capabilities. The timer is
aware of the crosstalk effects, making optimizations concurrent. It's
claimed to be at least 3X faster than that in Apollo and claimed to
use far less memory. The timer is common across all of the Avanti
back-end products.
* built-in HSPICE interface. Astro can write out HSPICE decks for
circuit simulation.
* capacitance models are non-linear (table-lookup) by default.
* crosstalk optimization, starting from placement. Optimization is
concurrent and preventive. Repair mechanisms include gate sizing,
buffer insertion and route modification.
* Rail analysis much like Mars Rail.
* A constraint checker - checks the quality of the constraints.
* They also made an effort to correlate the timing results with those
of PrimeTime. They claim that the timing is of tapeout quality.
* Built-in chip finishing capabilities.
Astro is fully integrated with their various analysis and optimization
capabilities. Therefore, one does not hear about Saturn, Mars etc.
There are no multithreading capabilities in Astro."
- [ An Anon Engineer ]
"We are basically a happy Avanti customer. We're using their current
tool set and expect the current tools will take use through 2002, and
possibly 2003 and 2004. We feel we can wait and see what emerges over
the next 18 months."
- [ An Anon Engineer ]
"Saw the demo from Synopsys on Route66 compiler and Clock tree compiler.
It sounds too good that just a few scripts can handle everything. They
claimed that it is in limited availability right now. I will be really
interested to hear comments from the test customers.
Astro's demo suite is 2 hour long. Compare to 1 hour for other EDA
vendors. Like the way that they talk about new CTS feature, where they
can do a better job balancing the inter-clock skew. We are using
Apollo right now. Thinking about switching to Astro."
- [ An Anon Engineer ]
"We have delibertly avoided Avanti backend tools for years because of
this lawsuit. How can I trust my designs and intelectual property
with a company founded by stealing someone else's intelectual property?
I am more interested in the Synopsys clock tree tool than Route 66."
- [ An Anon Engineer ]
"We are waiting to see if Avanti will be around. We evaluated Avanti
as our #1 choice especially since they are the standard with our
foundary. So we will simply work with outside vendors a bit more
and wait. Overall I think Avanti will survive and grow stronger
from this."
- Phil Kuglin, Credence Systems Corp.
"With regard to Avanti vs. Cadence, my sympathy for Cadence is somewhat
limited. Leaving the jokes about jail sentences aside, I would observe
that Cadence, along with other EDA vendors when they are on top, tend
to exhibit smugness, complacency, and a lack of innovation and
responsiveness to customer needs. I have no qualms about using Avanti
tools, particularly those unrelated to the offending products, and I
can only hope that a fair scheme for restitution can be worked out."
- [ An Anon Engineer ]
"While the court proceedings concern me, I haven't completely soured on
Avanti tools, and hope that they can rebound in the near future."
- [ An Anon Engineer ]
"OK, so Avanti stole the Cadence code to get started, so if both
companies had the same base to work from, and Cadence claims that it
put them in such an unfavorable competitive position, why are
the Cadence P&R tools so crappy and the Avanti tools so good?"
- Phil Hoppes, Intersil
"In talking with some of the place and route vendors, I heard an
interesting comment. The statement was made that you can't do more
than a few million gates flat with any existing router. When I told
them they were wrong, and that we were doing designs larger than this
flat, they said, "Oh, you must be using IBM tools." We are. It's a
shame IBM isn't in the commercial space for EDA tools - I believe
many of their tools could run circles around the "standards" that
the masses are using.
- Mike Berry, Silicon Logic Engineering, Inc.
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