( DAC 04 Item 2 ) ---------------------------------------------- [ 02/09/05 ]
Subject: Forte Cynthesizer
THE JAPAN CONNECTION -- While SystemC synthesis is considered playland
experimental stuff for most U.S. design teams, in Japan it's slowly being
considered as a serious design methodology for quick-to-market consumer
electronics designs. No, SystemC synthesis is not mainstream yet (hardly),
but it's not pure pie-in-the-sky either. Konnichiwa, Forte!
We are a Japan-based design consulting firm that supports various
large design activities with major Japanese electronics companies. We
have been looking into higher level or behavioral level synthesis in
chip designs for years now, and currently use Forte's Cynthesizer.
At first, there was Behavioral Compiler from Synopsys, and then
others. None of these tools produced satisfactory RTL code from a
C-language source.
From our point of view, the following points are important in higher
level synthesis tools:
1) Support of pipelined design
2) Ease in defining/creating interfaces to surrounding blocks
3) Tool processing speed and throughput
4) Quality of design, i.e. Cynthesizer produces compact circuits.
We were very surprised to find Forte Cynthesizer, because it cleared
all of our 4 criteria.
Cynthesizer takes SystemC models and automatically generates RTL code.
We specify constraints for performance, clock speed, area, and target
semiconductor technology library, so that Cynthesizer can produce
more optimized RTL.
We are now working with customers to actually use Cynthesizer in the
design process. With one customer we have coded up MPEG in SystemC.
From this source we were able to get working RTL code from Cynthesizer
within 2 months. Our simulation speed was about 300 times faster. We
also found debugging at higher level of abstraction in SystemC to be
quite productive... it increased overall debug-simulation cycle
throughputs.
Our Video/MPEG related decoder:
- 7000 lines of code
- Resulted in 500K gate equivalent
- Roughly 1/5 of RTL lines of code
- simulation ran 100x faster
- design time was roughly 1/2 of RTL design cycle
Areas where Cynthesizer still can improve:
1) From a 3-D matrix description, we were unable to generate multiple
memories. Instead, a single memory was generated. Also, we can't
quite synthesize memory w/pipe-line storing capability.
Cynthesizer seemed to add extra cycles during memory access, and
we had to specify the matrix if we didn't want memory generated.
Finally, Cynthesizer is limited to pipe-lined memory access
2) SystemC coding method and styles are being worked out, thus it is
not straight forward for design engineers to learn correct coding.
Also interface issues to SystemC are not completely clear cut.
You can't synthesize memory interfaces, or CPU interfaces that
have been connected.
Beyond just knowing SystemC, design engineers considering using
Cynthesizer must able to anticipate how coding affects resulting RTL
code... this isn't that much different from current RTL synthesis. But
because timing and cycles are abstracted, more detailed knowledge of
how resulting RTL is generated might be required. i.e. there is more
responsibility for the users.
- Hiroyasu Hasegawa of HD Lab, Inc.
Forte sells a tool that does from SystemC to RTL. The tool inserts
registers based on a separate constraint file. In order to know how
much logic it can do I a given period of time, it characterizes the
library for common arithmetic blocks. It also has a data path
synthesis tool and can characterize some parts on the fly.
- John Weiland of Intrinsix Corp.
Cynthesizer first translates behavioral SystemC (an untimed algorithm)
to RTL SystemC, and then it translates RTL SystemC to Verilog RTL for
logic synthesis. Beyond this, it automatically creates multiple RTL
implementations and optimizes them according to designer-specified
constraints/requirements, e.g. area, performance, clock speed, and
target semiconductor technology library.
This allows architectural exploration and can both aid in more thorough
implementation exploration, as well as potentially saving a great deal
of time.
Cynthesizer analyzes the functionality of the algorithmic design and
identifies all of the data and control dependencies. It automatically
generates a finite state machine to control the flow of logic between
a set of functional units that have been optimally scheduled to meet
constraints, such as adders and multipliers or much more complex
datapath components. It constructs RTL structures which keep the
variable FSM timing off of the critical path and help with timing
closure. It can also automatically unroll loops, flatten memories,
pipeline the design, and perform a host of other RTL design techniques
automatically. It also has an integrated datapath optimizer for high-
performance, low-area parts to further optimize the results.
The original behavioral algorithms are supposed to run anywhere from
10x to 1000x faster than typical RTL simulations speeding verification.
This is consistent with what I have actually experienced with SystemC
models of modestly sized systems. To validate the generated RTL from
Cynthesizer, Forte claims that the tools will automatically manage the
simulation of each RTL implementation with the original testbench
without changes. This seems important given that the RTL
implementations can be generated very quickly.
Forte also claims that their quality of results exceeds hand-coded
design -- specifically with timing & area optimization. This has been
a problem with behavioral synthesis in the past. For example, in the
demo Forte showed an imaging algorithm used in a consumer electronics
application. The tool quickly generated multiple RTL implementations
with thousands of lines of RTL each from the functional algorithm.
Using the exploration and optimization features, the tool was able to
reduce the area by 25% and improve the performance by more than 10% as
compared to the original hand coded designs. If this is true, it has
great potential.
No claims were made that this was the answer to all our behavioral
synthesis problems. In fact I saw no evidence that the technology
would be much help for the large-scale, control dominated systems on
which I spend most of my time. However, it was abundantly clear that
the tool had a sweet spot where it did an excellent job: algorithms
for complex data transformation of the kind that turn up again and
again in consumer products.
More speculatively, while RTL-coded IP is sometimes very hard to figure
out, let alone to adapt, reshape and re-optimize, having it expressed
in SystemC with a tool that can transform it to meet SOC-level
constraints while allowing for technology factors, may be a very
powerful means of delivery.
In an ideal world, I would like to see a constraints and estimators for
power in Cynthesizer. Additionally, more emphasis on memory support is
needed it.
The other problem is that SystemC-based flows currently lack good
tools for debugging, especially for bugs caught late in the flow that
need to be correlated with front-end design descriptions, constrained-
random verification and other really important flow hooks and point
tools.
- [ An Anon Engineer ]
Forte's Cynthesizer can actually convert high level coding to RTL.
This will help in terms of verification. We do have some issues while
verifying SystemC and C++ behavior models. I think their tool will
help close the loop with System models.
One weakness: when we convert from behavioral model to RTL, how can
we do formal verification? How about cross-clocks domains, i.e.
asynchronous clock domains; how will Cynthesizer handle that scenario?
I don't think Forte ever mentioned this. Our design has a lot of
cross-clocking path. So I'm curious and would like to know."
- Hien Nguyen of Skyworks Solutions
Forte Cynthesizer excels at exploring design tradeoffs. Given a range
of design parameters it will provide area and speed numbers. For
products with very short design cycles where designers are not looking
to wring the last few % out of a design it could be useful. It would
be a good tool for us if it supported a greater subset of C++ and could
explore power. And cheaper would always be better.
- Greg Tumbush of Starkey Labs
We are evaluating Forte Cynthesizer, Mentor Catapult C, and Synfora.
No final mark yet.
- [ An Anon Engineer ]
Looking at all. Forte has the lead, Celoxica is closing in fast, and
a dark horse will soon be entering the race that will surpass all.
- [ An Anon Engineer ]
I had a chance to use Forte's Cynthesizer and was impressed by the
results. The area/latency results I obtained clearly showed that it
can create efficient designs in less time.
- Gaurav Singh of Virginia Tech
Forte Cynthesizer -- done designs with this tool, but no silicon.
Forte claims a lot of things (very marketing aggressive), however they
still need to work a little bit to have some stable results on large
blocks. Their "C + pragmas" mixed description is very messy.
- [ An Anon Engineer ]
Just looking at these tools right now.
- Himanshu Bhatnagar of Conexant
We are looking at those tools. Concerning Celoxica, we think
that this is a much more HW coprocessor approach, based on a PC
architecture with a closer look to the HW resources.
From our point of view, Forte allows a better "platform independent"
approach staying closer to the standard SystemC approach.
- Jordi Carrabina of the University of Barcelona
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