( DAC 04 Item 8 ) ---------------------------------------------- [ 02/09/05 ]
Subject: Synplicity Certify vs. Synopsys DC-FPGA
BIG BROTHER -- Synopsys is now trying to break into Synplicity's home turf
of the FPGAs-to-prototype-ASICs tool biz, but Certify seems to be holding
its ground here (for now). I wonder how this fight will look a year from
now. Both companies have strong vested interests in this space.
Synplicity Certify
The main problem for FPGA prototyping is the design partitioning,
because unfortunately your design will not fit in one device.
We use Certify since the late 1998's in all our FPGA prototyping
projects. FPGA prototyping is not a simple task, because you have
to take into account your HW resources:
- FPGA Board resources (# of FPGA's, traces etc..)
- FPGA resources
- ...
This is the point where Certify comes into the game. Certify helps
you to spilt up your design on your FPGA board. You can import a
Verilog description of your board into the tool and with the build
in "area estimation" you have all important information necessary
for partitoning. There are other features which helps you to save
board or FPGA resources (e.g module replication, zippering ..).
In the case of design partition, so that we could succesfully setup
protoptying systems with up to 10 FPGA's.
In my point of view Certify is a must in case you have large designs
to prototype.
- Gerhard Pletz-Kirsch of Philips Semiconductors GmbH
Some exposure to Certify and DC-FPGA. IMHO, Certify is the industry
leader. It supports multiple FPGA solutions and has decent synthesis
results.
- [ An Anon Engineer ]
We have used Synopsys FPGA Compiler and Leonardo from Mentor before.
For 2 years now we are using Synplify Pro and Certify from Synplicity
and we are very happy about them. They work several times faster than
Synopsys and Mentor and you get better results (higher frequency) after
FPGA synthesis. We have shorter turn-around times and better results
with Synplicity. And it is very comfortable for ASIC prototyping.
Leonardo always crashed with our big designs, and Synopsys didn't make
any efforts for FPGA in the last years.
- Christian Nuk of Micronas Semiconductor
What I have seen when Synopsys people present us DC-FPGA, they are far
behind Synplicity.
About Certify strengths/weaknesses, notice that we use Certify in
limited way (we don't stress tool to much, because when we did this,
we run into many tool problems. Due to small number of customer,
Synplicity doesn't have to many people working on this tool, so fixing
of problems we found wasn't that fast.
We mainly use Certify for partition on predefined boards.
- Impact Analysis is one of the biggest strength in Certify. Area
estimation is sometimes far away from reality. The rest of this
feature implementation is perfect.
- Pin multiplexing (CPM) is second great feature in Certify. It isn't
perfect (for example, deal with combinational feedbacks and snakes is
something about Certify doesn't give you any support - Certify people
promise some improvement there before 1.5-2 years, but I have not
seen anything what could be used). Also, concept of synchronous and
asynchronous CPM isn't implemented well at all. But Certify is open
enough (enable you to make custom CPM cells) and we found a way to
get tool support for what we need.
Overall concept of Certify is good. As usual, problems are in details:
- Using of Partitioning tool separately of synthesis tool is the
preferable way for us, but Synplicity people don't like this too much
(probably because you could use any FPGA synthesis tool afterwards).
When you use Certify in this way, there are lot of problems related
to Assigning of Logical Nets to Physical Traces, luck of any top-level
design budgeting (approximation could be good enough), project options
and constraints for separate projects for each FPGA.
Nothing of this problem exist when you use tool in push-button way
(partitioning + synthesis for all FPGAs at once), but everything
is 2+ times slower (probably because of top-level design budgeting)
and sequential (you could not synthesize all FPGAs in parallel
with multiple Simplify licenses for example).
- When you run into some Certify problem (and it is not rare at all),
you don't have absolutely any information why problems appears.
You get Error Message like: "Call Syplicity Support" and Syplicity
guys always ask you for your design to reproduce the problem.
Then you are trying to reproduce problem with some dummy design.
Tool development isn't our job, some meaningful Error Message would
be nice.
- Assigning of Logical Nets to Physical Traces is implemented in a way
that you hardly could avoid using of GUI in this process (when
connection changes).
- There are lot of small problems when Certify deals with bidirectional
pins, with tied_to_1/0 propagation through partitioning boundary.
You could compare connection requirements when you replace some
module with dummy version - all outputs tied to constants and few
inputs routed to outputs - with version when you really remove module
from RTL code.
- Forward propagation of timing constraints and other things to FPGA P&R
tools is poor and with lot of bugs (it is both Synplify Pro and a
Certify problem.)
Our overall impression about Certify is more than good. Whenever
we look into competitive tools, conclusion was that Synplicity
is far ahead.
- Vladan Andrijanic of ATI
Synplify Pro - Only complaint we have is that it doesn't always
create an EDIF that will time in the backend but, rerunning it
always creates an EDIF that times. Go figure.
DC-FPGA - Synopsys did an eval for us on an existing design
(133 MHz Virtex II Pro) and couldn't do better than Synplify Pro.
They wouldn't give me the backend timing report (only the DC-FPGA
report) so I'm not sure how well the tool really did.
Exemplar - Never used.
- Don Monroe of Enterasys Networks
We have tried Synopsys DC-FPGA, Mentor Precision, and Synplify Pro.
DC-FPGA was a joke. The tool fell over at every stage with our
test designs. A Synopsys support engineer even commented "Why are
you using that?"
Precision seemed OK but with some bugs. Again Mentor seemed very
good at providing support on these issues, providing workarounds in
a timely manner.
Synplify Pro was the easiest tool to use, ran faster and produced
marginally better results (~2% smaller except in one case where
Synplify produced a design with ~20% more gates than Precision.)
- [ An Anon Engineer ]
I've been using DC-FPGA for two designs. The first was a pure FPGA
design, the second is a FPGA prototype.
I really like the ability to control the FPGA synthesis in the same
manner as I do with Design Compiler, i.e. that the scripts are almost
identical. You can even do something like:
set gIsFPGA 0
if {[info vars Synopsys_program_name] != "Synopsys_program_name"}
{
puts stderr "WARNING: Run this script using a Synopsys shell"
} else {
set gIsFPGA [expr {"$Synopsys_program_name"=="fpga_shell"}]
}
Then you can do stuff like:
if $gIsFPGA {
report_fpga
}
within your scripts and use common scripts for your FPGA and ASIC flow.
DC-FPGA is also very fast. We observe more than an order of magnitude
speed increase on DC-FPGA on our Opteron systems compared to our old
hardware running FPGA Compiler II.
- Petter Gustad of Dolphin Solutions
For FPGA prototyping DC-FPGA is propably the best bet. For
developments targeting FPGAs, I'd go with Synplicity.
- [ An Anon Engineer ]
We use only Synplicity Synplify Pro and Altera Synthesis for FPGA
designs. For us, Synopsys DC-FPGA is not accurate for FPGA design
and we don't use it.
- Gerard Chartie of Alcatel
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