( DAC 04 Item 10 ) --------------------------------------------- [ 02/09/05 ]
Subject: ViASIC and Synplicity Structured ASIC
THE NEW MONEY -- Like a circus barker selling snake oil, the new supposedly
next wave breakthrough technology is "Structured ASICs". (Which is just
a SpongeBob fancypants way of saying the words "Gate Array"; but hey, if it
brings new revenues in, who am I to criticize?) Anyway, the so-called "big"
player in this niche is Synplicity and it's friend, ViASIC. (It's not a
big niche so far -- 4% of designs according to the DAC stats.) Synopsys,
Mentor, and Cadence are pretty much taking a wait-and-see approach here.
I have seen ViASIC demo at DAC, and found it quite interesting. ViaPath
looks like a full solution tool, including clock tree balancing, what
they call "placement", and powerGrid. Comparing to regular ASIC, it
is a safe way to get your first chip done with no need to face the
process issues, or corner related problems. (The structures are pre-
characterize.)
However, pre-placed objects are not cost (area) effective, and the clock
grid methodology for balancing the clock fits to full-custom processors
which need small skew. This is not to most of the ASIC applications
that need the low power design. Timing convergence issue, mainly setup,
looks hard to achieve here, too.
I'm not sure if someone has thought about this before, but I would be
very interested in a Structured ASIC block which is basically an IP
that I can place in our ASIC, and can be used for datapath, and spare
logic (which can be later used by changing one mask).
- Eli Assoolin of Transchip
I saw the ViaPath demo in DAC 2004. I feel it's a great tool. It has
a very simple user interface and can complete the entire physical design
by a few clicks. Though I have several concerns.
1) I don't know how good the timing ViaPath can achieve since there is
neither comparison with other tools nor comparison w/ other fabrics.
2) For the fixed routing structures, I believe routability could be a
serious problem since routing resources are much limited compared to
customized routing. ViASIC has half of cells for memories, which
could relieve routing problem since memorys has low interconnect
complexity. But on the other hand, how the fixed memories fits with
various designs is still not clear to me.
3) The efficiency of ViaPath hasn't been justified. We ran a small
design using 30 min. How ViaPath scales is unknown to me. Due to
limited routing resource, it could be much more difficult to route
for some designs with high interconnect complexity.
I think the whole Structured ASIC idea is a good one since the gap
between Standard cell based ASICs and FPGAs is still large. By
providing the trade-off between single-via-mask fabric to
several-metal/via-mask fabric, designers can try the best match for
cost/performance consideration. A tool which can quickly evaluate
different trade-offs could be very valuable.
- [ An Anon Engineer ]
We recently evaluated ViASIC as a way to a quick chip with low NREs
since ViaMask requires only one single via customization layer.
I was impressed by the ability of the ViaPath Place and Route tool
to complete the mapping of a very congested design (~91%). Their
TCL interface needs to be improved to support more user defined
customizations as well as library support. Memory cuts generator
is not so intuitive.
We plan to use ViASIC for the next projects.
- [ An Anon Engineer ]
The ViASIC demo looked interesting and worth trying out. I think the
Structured ASIC idea is a very good for some types of designs when:
- High percentage of design is known, and only a small part varies
- Need to optimize TTM vs. price
- For ViASIC: when the memory is not sensitive to noise
We use a sort of Structured ASIC idea (actually gate array) when we need
to tape-out very quickly with LOTS of generic spare cells that can be
configured (using metals only) to different types of gates. This allows
many fixes (bugs & features) to be done in metal only.
- Ronen Hasnes of Nationa Semiconductor
For Structured ASIC, I don't know too much about it. As for our
CAD group, we are interested in it. But we don't have a concrete
plan for it.
- Xiaoyun Sun of Qualcomm
You asked about my thoughts on the whole Structured ASIC idea. I've
looked at various vendors (Easic, Atmel, Virage, Leopard Logic, LSI,...)
and read all the recent trade rag press. I think there's a lot to it.
We have kicked the tires on it here as well.
You have to decide first the problem you want it to solve. Is it for
prototyping, reducing mask cost, gaining some silicon flexibility,
providing multiple similar-but-different versions quickly, fast spins,
or picking a spot between FPGA and full ASIC? Depending on the
question, the answer may vary. For now, I'm researching this
technology. Based on that, I'll know what size investment to make
(time and money) moving forward.
- Dale Donchin of Analog Devices, Inc.
I am very much an advocate of Structured ASIC. I have written several
of Sandia's internal reports and proposals on this subject.
I have done some research before I decided to license ViASIC's One-Mask
Structured-ASIC technology. One of the major reasons is because Bill
Cox, CTO of ViASIC, has been a pioneer in structured ASIC architecture
research and tool development. He was involved in the early development
of many commercial Structured-ASIC products available today. ViASIC is
a small company. They are not in the market to sell silicon like others
Structured ASIC companies. As such, they are easier to work with to
develop new products. (Sandia is interested in radiation-hardened
Structured ASICs. We have many special considerations that are
typically not important to other applications.) However, ViASIC has
limited resources. Their ViaPath tool does not have elaborate features
as others, but it is very well designed for the One-Mask architecture.
ViASIC is also very responsive to our need when we encounter problems.
We are still in the middle of developing the rad-hard Structured ASIC
base array. We have not fully verified ViaPath's features yet.
However, my engineers are generally happy about the tools capability.
- Kwok Kee Ma of Sandia National Laboratories
Regarding Structured ASIC: I believe that there is not a winning
technology in this area due to the nature (and complexity) of the
specifications that comes from real designs. The challenge for the
future will be to find the right mix of IPs with some mask-configurable
logic around in a platform-based design context.
- [ An Anon Engineer ]
From a general point of view, eSilicon believes that Structured ASICs
will become more popular at 90 nm and below. At .13 micron, the
economics of stocking base arrays doesn't quite work. As densities get
higher, mask costs get higher, and transistor "cost" goes down, these
approaches make more sense.
- Mike Gianfagna of eSilicon
Structured ASIC definitely has a role, seems to be at last gaining
serious traction. Interesting space to watch.
- [ An Anon Engineer ]
It is our concern to use Structured ASICs for our small-lot products,
so we are researching tools for them.
- [ An Anon Engineer ]
Synplicity is good
- [ An Anon Engineer ]
I like tools from Synplify very much, easy and powerful.
Structure ASIC will be dominant.
- [ An Anon Engineer ]
I don't particularly trust Synplicity outside the FPGA realm, but
Structured ASIC is pretty close.
- [ An Anon Engineer ]
I think Synplicity tools like Amplify/Certify is better than others
and faster than others.
- [ An Anon Engineer ]
Synplicity Amplify ASIC: I evaluated this tool sometime last year and
because it did not have the capability of register retiming (our
design required that), it couldn't meet the speed. We gave up on it.
- Himanshu Bhatnagar of Conexant
Index
Next->Item
|
|
