( DAC 04 Item 17 ) --------------------------------------------- [ 02/09/05 ]
Subject: Sierra Pinnacle
MAGMA WANNABE -- let's see... A bunch of ex-Synopsys PhysOpt developers
drop out to form their own EDA company. Pravin Madhani, their CEO, is the
most searched name on DeepChip for 2 years in a row. And two users in
ESNUG 435 #3 post their hands-on Pinnacle tape-out stories. All that's
left is for Sierra to get into some sort of lawsuit with Synopsys, and
they've become the new Magma! Watch out, Rajeev.
All joking aside, Sierra faces 3 serious problems:
1.) If you look at the 9 users comments on Sierra below, 8 of them are
"tire kickers"; they're not actual customers, just people interested
in looking at Sierra. Sierra needs hands-on users and needs to get
these same users to publically speak up on its behalf.
2.) If you look again at the 9 users below, they're all Indians. Sierra
was founded by Indians. For Verisity, it was Israelis. For Silicon
Canvas, it was Taiwanese. No biggie, but Sierra needs to diversify
its employee and customer base if it wants to sell to a world market.
3.) In the EDA community there's a suspicion that Sierra was formed as
a short term company designed to be acquired by Cadence or Mentor.
Sierra has to shake that image or it'll stunt their growth.
Once Sierra slays these 3 dragons, then it'll be a viable new Magma.
I visited Sierra's DAC booth last year. They claim to handle up to
10 million gates on a 32-bit Linux platform. They also promise better
quality of results when optimizing for 90 nm effects including low
power, SI, and design variability effects. Pinnacle is on my list of
tools to watch in 2005 for our 90 nm designs.
- Jagesh Sanghavi of TenSilica
We have been planning to look at Pinnacle and explore integrating it
into our flow. Pinnacle's claim of 10 M gate flat capacity in an
overnight run time can definitely help us run large designs flat.
- Venkata Simhadri of Time-To-Market, Inc.
I saw Sierra Pinnacle at DAC '04. Sierra Pinnacle's claims about
capacity, runtime, and reduced iterations are definitely worth
considering. Their macro placement / prototyping capability also
sounds interesting as not many other vendors have that well
implemented. We plan to look at Pinnacle at the next overhaul of
our physical synthesis flow.
- Amit Chandra of Broadcom
Up to 10 million gates in an overnight run should help us extend the
life of our flat flow methodology. If we can do bigger chips flat and
reduce the number of iterations/time per iteration, we can do more
chips with our existing back-end resources. For us that is something
definitely worth looking at.
- Rajesh Shah of Open-Silicon, Inc.
I was quite impressed with Sierra's Pinnacle suite demo at DAC last
year. They seem to have addressed most of the issues with the current
EDA place and route tools and promise to give the best performance in
the shortest possible time. Integrated placement, optimization, trial
routing, CTS, and prototyping built into a well designed database &
timing infrastructure in addition to very high capacity and very fast
iteration items.
- Syed Ahmed of Oki Semiconductor
I was quite impressed with what Sierra was able to achieve in such a
short time. They are tackling very hard problems such as low power
optimization and signal integrity analysis, at the same time being able
to deliver the performance and capacity. I would like to see Sierra
put more effort in the area of AMS in terms of being able to seamlessly
port "analog oriented" constraints into a digital context and perform
the required synthesis optimizations.
- Rajesh Berigei of National Semiconductor
What sets Sierra apart from the other tools is not only fast run times
but the multi-corner, multi-mode hold fixing abilities of this tool.
- [ An Anon Engineer ]
I visited Sierra's booth and saw their demo on Pinnacle. Tool aims to
address "very large" ASIC blocks and probably competes in the same
space as SNPS's PhysOpt, Magma's Blast Fusion, etc. They claim to
enable very large scale physical synthesis. Sounds interesting as we
are continuing to see significant growth in sizes of blocks that we want
to handle as one P&R module where capacity and QoR are equally important
needs. We might consider taking a closer look at a later date.
- Zia Khan of Intel
We talked to the Sierra folks at DAC 2004 in San Diego and were
impressed with their claims about high capacity, fast runtimes, and
QoR. We followed up and did an evaluation.
We used the Cadence First Encounter placement software to meet
our "functional" mode setup and hold times, and followed that up with
extensive timing analysis flow and ECO generation scripts to verify
and fix hold time in other modes such as BIST mode, scan mode etc.
Compared to Synopsys PhysOpt, the run time of Pinnacle was better by
an order of magnitude -- several hours for PhysOpt vs. several minutes
for Pinnacle.
We were impressed by Pinnacle's simultaneous analysis and optimization
at multiple-modes / multiple-corners capability.
Pinnacle also provided faster timing closure for blocks and chips by
eliminating time consuming manual iterations using scriptware for
various design modes.
After the evaluation, we analyzed all the pros/cons of all three
tools (Pinnacle, PhysOpt, and FE), and decided to continue with the
Cadence First Encounter platform for our 90 nm chip.
- Atul Bhagat of Azul Systems, Inc.
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