( DAC 04 Item 19 ) --------------------------------------------- [ 02/09/05 ]
Subject: Cadence First Encounter, Silicon Dimensions Chip2Nite, Icinergy
THE BLOODBATH -- Ever since Cadence acquired First Encounter, there's been
a slow but sure bloodbath in the floorplanning/estimating market. Like
poisoned fish, InTime, then Monterey, then AmmoCore all went belly up. And
at the end of 2004, the CEO of Tera Systems suddenly and spontaneously left
his Tera. In this space ruled by FE, remains Icinergy, Tera Systems (still)
and Silicon Dimensions Chip2Nite. Tough neighborhood.
We have a couple people using the Icinergy (now called Javelin)
SoCarchitect tool. It gets good reviews from the users (very
versatile) and it can output floorplan information in the Cadence FE
format. Used mainly by chip architects to communicate their chip
layout requirements to the physical design team.
- Robert Cram of Gennum Corp.
Tera Systems has pre-characterized libraries of large blocks (like
adders and multipliers) that allow them to quickly estimate size and
speed of various design alternatives. New for this year, you can
characterize a new library in about an hour. They have finished
their place and route engine for virtual prototyping and support any
number of hierarchy levels. They now support VHDL and Verilog,
including Verilog 2000. They want to spot the big problems before
you are too far down a particular path. Customers say they are within
10-15% of final results, which they say is their goal. They are proud
that IBM requires their tool if a customer is doing RTL handoff.
Silicon Dimensions sells a design planning tool that his a wire-centric
placer and virtual router. It provides frontend designers with fast
information about things like fan-out and number of logic levels so
they can iterate RTL without tying up expensive back end licenses.
Their placement can be used as a seed for PhysOpt. One benchmark they
quoted was a design that using PhysOpt-Astro alone took 14 hours, but
with a 1.5 hour run on their tool, it then took only 2 hours on
PhysOpt/Astro (3.5 hours total).
- John Weiland of Intrinsix Corp.
Our experience with Silicon Dimensions Chip2Nite was that it was not
able to generate an optimized floorplan superior to our existing ones,
generated through manual design and in the Magma flow, for a 130 nm
design. My impression is that Blast Plan, First Encounter, and
Jupiter-XT would provide better results (and are also vastly more
expensive).
We did think Chip2Nite has potential, and the staff was very responsive
in resolving the Verilog errors we reported. Its ability to view and
alter DEF files, and quickly display various checks and statistics
about our design was useful in working with physical designers.
Chip2Nite is relatively easy for RTL designers to master.
Because we do not have back-end tools in house, we are seeking a general
purpose floor planning tool which can interface to Synopsys, Cadence,
and Magma. We may well re-evaluate Chip2Nite in the future.
- [ An Anon Engineer ]
To solve the placement/routing layout problem, Silicon Dimensions has
been forced to build an entire placement engine. When I first met them,
I said that unless I could hand off that layout to my backend flow,
their results were meaningless. Their final placer could use an
entirely different algorithm. They addressed that problem by allowing
the handoff. I still wonder how accurate the real placement can be
without the real floorplan and power gridding in place.
I also wonder how much credibility Silicon Dimensions has as a placement
engine when Synopsys, Cadence and Magma throw at least 10X the people
at this part of design. I think placement is one of the hardest parts
of the overall problem, at least to do well.
The Chip2Nite tool does have some really nice features for analyzing the
placement and layout and to help give the front end guys a better idea
of what their design issues are. I haven't used them, but that is my
impression from their presentation.
- Cary Robins of ChipWrights, Inc.
We use Synopsys Floorplan Compiler (FPC).
- [ An Anon Engineer ]
I use PKS/Encounter daily and still think it's the easiest way to get
produce a medium-sized chip. It may not be perfect (what is?) but
it's highly scriptable and very consistent. In a single script I can
go from RTL all the way to a DRC clean DEF file -- no menus, no GUI,
no other tools required. And it only takes me a day or so to adapt
my script from one chip to the next.
- [ An Anon Engineer ]
I use Cadence FE as my floorplanner (sometimes to floorplan for PKS).
It's OK. It's easy to use and does the job, but it seems difficult
to script and get repeatable results. I hate that. I usually end
up placing before remembering to insert power or forgetting to click
correct width/height button in the floorplanning GUI, then having to
delete everything and start from scratch.
Cadence either needs to learn how to design a GUI or just give up.
Maybe they could see if Apple offers an overpriced training-course
on GUI design. :)
- [ An Anon Engineer ]
Cadence First Encounter is easy to use. Jupiter-XT is hard coz of
Scheme language.
- [ An Anon Engineer ]
The jury is still out on whether Encounter 4.X can close timing on
timing critical designs. Otherwise, the tool has become really stable
over the years and works really well in handling big designs. We still
use PKS to close timing on blocks and it has worked out well. We used
PKS/Encounter combo for several tape-outs last year.
First Encounter is our floorplanning/SVP tool and has worked very well
for our designs.
- Mani Gopalakrishnan of Fujitsu
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