( DAC 04 Item 37 ) --------------------------------------------- [ 02/09/05 ]
Subject: Orora, ADA, CiraNova, Barcelona
MIXED-SIGNALS -- Analog synthesis is one of those tools that its potential
customers give you mixed signals on. (Pun intended!) On the one hand,
engineers like the idea of automated tools to help them. On the other
hand, the engineers feel that analog design is The Black Art Which Can't
Be Automated -- and that analog synth tools will only just make more work
for them (because they'll be stuck cleaning up after the tool's messes.)
Analog synthesis is an ugly, evangelical sell.
Nothing new here except Orora, which has the first commercial automatic
analytical solver for analog designs based on symbolic representation.
Barcelona finally comes up with their own solver that don't rely on
their service to generate models on customer circuits based on their
geometrical-programming based flows. These kinds of technology should
dramatically change the way prople do analog designs, with more
insights into any given circuit topology. It'd be very interesting to
see how they will evolve over the next couple years.
- Weikai Sun of Volterra
Orora Design Technologies sells an analog/RF synthesis tool that takes
an un-sized netlist and measurement criteria and provides a sized
netlist for you. They also sell an analysis tool that may be unique.
The user provides a SPICE netlist, models and characteristics in which
they are interested, and the tool creates an analytical equation
describing the equation, which can then be examined using their GUI
for pole/zero analysis, sensitivity, Monte-Carlo analysis, etc.
- John Weiland of Intrinsix Corp.
Orora Arsyn
I had both a booth and suite demo from this start-up. Their Arsyn tool
is a SPICE-based circuit optimizer which accepts multiple topologies,
specifications and a technology file. It works with any SPICE
simulator, and outputs a sized-netlist plus behavioral models in
Verilog-A or VHDL-AMS format. Simulation results are presented with a
Circuit Performance Radar chart, showing which specs have been met and
which are out of spec.
Constraints are entered via a spreadsheet dialog. Arsyn choose from
among your multiple topologies to choose the one that best meets your
constraints. Arsyn is integrated in Virtuoso and has its own pull-down
menu choices. A user may specify how every MOS device is to be varied
across a range of values during sizing. The demo example was a four
stage VCO which required 8 hours to create an optimized netlist.
Multiple SPICE licenses may be used at one time to decrease the run
time during sizing.
Arana accepts a schematic netlist, and the user defines relationships
like Vout/Vin to specify a transfer function. The tool creates an
equation automatically for this transfer function. Sensitivity
analysis can be performed after equations are created. The equations
are for small-signal behavior, not large-signal behavior.
Arsyn the circuit optimizer either uses SPICE results or Arana results
for sizing. A switched-cap filter demo showed a visual Pole/Zero
analysis after Arana was run. Component sensitivity plots are quickly
generated. Monte-Carlo analysis based on small-signal analysis
was also shown.
Arana should be used to create a better starting point for a netlist
prior to running Arsyn. A bandpass filter example required 1371
SPICE simulations when just using Arsyn, however using Arana results
then only used 43 SPICE simulations in Arsyn. An opamp example
required 252 SPICE simulations with just Arsyn, while using Arana
first only required 22 SPICE simulations in Arsyn.
Orora is only looking at the front-end issue of transistor-sizing,
and they don't provide automation for analog layout. Their DAC booth
matched their web site -- both were amateur.
Competitors say that Arana only works for opamp circuits, and is not
useful for other real analog circuits.
- Daniel Payne, Consultant
We've been productively using the ADA "Creative Genius" tools
(subsequently acquired by Synopsys and renamed to "Circuit Explorer")
for about 15 months. We started off as a beta site for some of the v2
features last year, and are now a beta site for the pending v3 release.
This tool very effectively handles the process of closing an analog
circuit design across a very large number of design corners (typically
in excess of 150 corners in our environment). That's a big deal. In a
flow that's not based on an optimization tool it's quite typical to
somewhat readily achieve decent circuit performance at nominal and a
couple of other representative corners, and then spend a very large
amount of time trying to hold that performance across all required
corners. That tedious and ultimately unproductive manual process is
something which Circuit Explorer addresses very well.
Circuit Explorer doesn't in any way eliminate the need for experience
and insight in an analog designer. You still have to pick the desired
circuit topology, specify device matching constraints and legal
operating conditions, set reasonable design goals, define test benches
and measures that adequately "expose" those design goals, evaluate
multiple sized circuit candidates, etc. You'd do the same things in
any good simulation-manager environment, such as the Antrim (Cadence)
Aptivia tools which we used previously. But in return for the effort
of setting up all those items in Circuit Explorer you also get full-
fledged design optimization capabilities. In our experience that adds
major value to the analog design process.
Circuit Explorer very actively displaces any need for a separate
stand-alone circuit simulation manager. Optimization inherently
includes simulation management, but not vice versa. That's a key
point. You really want to set up the required constraint, etc.,
environment around each analog block only once. It takes way too much
time and effort to do twice. In our design flow we start early with
Circuit Explorer and then stick with it all the way through automated
characterization and documentation of the final selected optimized
block. That's something you can't do with separate simulation manager
and optimization environments.
We use Circuit Explorer in conjunction with Cadence Composer schematic
capture, with Sandwork's Spice Explorer waveform display tool, and with
HSPICE circuit simulation. In effect Circuit Explorer acts as a primary
analog design cockpit that our analog designers work within, while still
taking advantage of external tools for convenience (Composer) or for
quality (Sandwork). It's a very effective analog design combination
that'll get better still with the next (pending) Circuit Explorer
update. There's some good stuff coming in that release.
- Mike Carter of Potentia Semiconductor
ADA (Synopsys)
The new product name is Circuit Explorer changed from Creative Genius.
Circuit Explorer is a SPICE-based circuit optimizer with integration
into the Virtuoso (Cadence) or Cosmos (Synopsys) environments.
Optimization occurs across all PVT corners. A project viewer shows
the flow of the tool and all resulting optimizations. Constraints are
entered in a spreadsheet dialog, or imported from Artist schematics.
Testbenches define constraints.
The user specifies design variables for how each transistor may be
sized with min, max and grid step. Cross-probing between Virtuoso
schematic and constraints looked useful. Devices could be grouped
graphically to set group constraints. Device Operating Constraints is
a dialog box that can be filled out. Design constraints are entered
in a tree widget dialog like Id=20ua. PVT definitions are entered into
a spreadsheet. Goals or constraints are entered into a dialog in
columns like: max, min, poor, spec, priority.
Results from Circuit Explorer are viewed in a tool called IP Explorer.
You may dynamically update or change your constraints during
optimization which in turn effects what simulations are launched.
Training typically requires only one day of on-site expertise.
A netlist with 150 devices can be optimized overnight when using
10 CPUs. LSF can be used for load sharing.
- Daniel Payne, Consultant
I haven't seen any useful analog synthesis tools yet.
- [ An Anon Engineer ]
Analog synthesis is still pretty useless.
- [ An Anon Engineer ]
CiraNova:
CiraNova is a new startup made of people leaving Cadence and CCT, a
full schematic and layout environment that competes with NeoCell but
having and interactive environment. This year CiraNova changed focus.
Their new flow is actually the old ACPD from Cadence but with a lot
more usability. The idea is that an experienced group of people works
to setup for each type of analog constraint (i.e. symmetry, centroid,
interlaced, equal load, etc.) a template, or a layout architecture
that will be represented by a schematic annotation. Once all the
types exist every designer/layout can explore different architectures
by automated or manual placement and automated routing.
The time to generate a full OPAMP is 5-10 minutes. Each standard
defined architecture is fully integrated in Cadence and can be
modified at any time. A few CiraNova features:
- Easy placement based on schematic architecture - capture
architecture for future reuse.
- Read Cadence schematics into their schematic and
exports/imports Pcells.
- Legend - for types of constraints dynamic layout objects.
- Constraints driven net - R, C, vicinity to others, special
shield, etc.
- Fly line - has actually real value based on Manhattan calculation.
- Automated matching reports for each group of devices.
- Full back annotation of structure, parasitic (2-D values) into
Cadence - including cross probing.
- Process gradient layout - takes automatically care of process
issues based on technology file setup.
- No router yet so they call on Internet CAD router or CCT or
(maybe Pulsic Lyric?)
CiraNova changed focus to let customer set his/her own type of
architectures, last year they were pre-defined. Good change but
unfortunately Cadence NeoCell is running strong in almost the same
direction, and they can always improve on usability.
- Dan Clein, author of "CMOS IC Layout"
CiraNova
This start-up has analog luminary Jim Solomon as a sponsor. Entrance
to their suite was by invitation only. I spoke with Jim Falbo, tool
developer. The CiraNova focus is on automating analog layout in the
Cadence environment. They don't address transistor sizing,
optimization or synthesis. They would compete with NeoCell (Cadence),
Paragon, Mentor SDL, and Sagantec.
Anasift
Ampso, priced at $150K, is a simulation-based optimizer. A circuit
with 12 bits and 80 million samples per second can be optimized
in 24 hours. You can optimize across unlimited PVT corners. Their
symbolic-driven Monte Carlo analysis is faster and more accurate than
simulation-based Monte Carlo.
The Ampso optimizer produces a sized netlist. An opamp can be sized
in one day (24 variables, 306 constraints, 18 CPU hours). For
optimization runs just use a few PVT corners, not all corners.
Corner PVT verification is separate from optimization.
Barcelona Design
Last year Barcelona had analog IP generators that used equation-based
optimization. This year they opened up and are offering equation-based
language, libraries and optimization. This technology is very
different from simulation-based optimization because it determines
an optimally sized transistor netlist that meets all specs.
You must learn a new language with Barcelona to describe the analog
behavior, but it doesn't require a compute farm to produce an optimized
netlist. Their approach also handles the largest analog designs like
PLLs and converters. Optimizing a PLL takes only minutes to an
hour or so using a single CPU.
- Daniel Payne, Consultant
Barcelona Design sells an analog synthesis tool (netlist to sized
netlist). Their approach is unusual in that it is equation based. It
derives equations for whatever parameters are of interest and then
solves those equations for transistor sizes. Prior to this they had a
fixed library of circuits that they could synthesize and actually
produce layouts for, but it sounds like they are de-emphasizing this
aspect and emphasizing a more general purpose tool.
- John Weiland of Intrinsix Corp.
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