( DAC 04 Item 38 ) --------------------------------------------- [ 02/09/05 ]
Subject: NeoLinear NeoCircuit & NeoCell
TWEAKERS -- I ran into an analog buddy at this year's DAC and he called the
NeoLinear tools "tweakers", in that they tweak transisters for you. "I'm
here because my boss wants me to look at this year's crop of tweakers. He
may actually buy something, if I can talk him into it."
NeoLinear (Cadence)
NeoCircuit:
I saw 2 suite demos to see both NeoCircuit and NeoCell. Both sessions
were well attended, and the presentations were professionally delivered
and compelling. In the NeoCircuit DFM session they emphasized that
NeoCircuit will optimize transistor sizes and center your small analog
designs like an opamp. Simulation measurements versus specifications
are shown graphically.
Renasas showed an 8x productivity improvement with NeoCircuit. The
design flow is to first define all of your variables with acceptable
ranges, setup your simulations (AC, DC, Transient), then watch the
results from simulation.
They have auto matching algorithms to analyze your netlist and
determine all matching devices without intervention. Matlab compatible
functions can be re-used as new goals in NeoCircuit. Operating regions
can be used as constraints. The optimizer sizes devices across PVT
corners using heuristics, launching the minimal number of simulations.
Monte Carlo simulations are run under the DFM menu. Device mismatch
simulations can also be launched. Parallel Charts visualize the Monte
Carlo results. The worst case PVT for any goal is automatically
identified. A large design like a PLL would have to be broken up into
pieces for use in NeoCircuit.
NeoCircuit has inputs like variables, device and design constraints.
The user defines a range for each design variable. Goals are specs or
operating regions.
A compute farm is recommended for NeoCircuit and Spectre has a special
pricing for something called Burst Licensing to keep the costs low.
Simulations may be AC, DC or transient jobs. LSF can be used for load
balancing, or you can use a Neolinear technique. Optimization results
may be visualized as they are generated then you can filter out what
you don't need to focus on a few. Most designers use up to 50
variables maximum, and lots of specifications. A customer example had
6,000 transistors with 250 constraints, running overnight to optimize.
NeoCell:
NeoCell is an APR system for analog circuits useful for IP reuse,
retargetting and IP migration. This methodology is 5x faster than
traditional full-custom layout. Cadence Pcells or Neolinear ModGens
can be used by NeoCell. Toshiba is a reference customer claiming
technology migration in just days for a new process. ST is another
reference with benefits of 5-10x productivity improvements for analo
migration.
NeoCell has layout matching and layout symmetry features. There's a
constraint editor which allows layout grouping, and guard ring
automation. Their tools also automatically identify symmetrical
transistors. Net symmetry is automatically identified. Pin symmetry
is auto identified. Device constraints may be entered graphically.
Mapping of schematic to layout devices is automatic, and fingers can
be defined. Selection of wells is automatic or manual. Device
orientation is selectable. Wire style is process independent. VDD/VSS
can be constrained to not use poly, only metal layers. Location of
VDD/VSS can be constrained like Top/Bottom. Width of VDD/VSS can
be specified as 20X minimum. Analog layout is automatic following your
constraints.
There are three different constraint editors at Cadence: Artist,
Neolinear, QDAI. Each layout tool has its own technology file, they
are not the same. DRC errors are automatically fixed. The analog APR
is not merged with the digital APR tools. Artist has schematic driven
layout, but no compactor like NeoCell.
RAD:
Cadence has a flow called RAD, rapid analog development. NeoCircuit
and NeoCell are the tools for RAD. NeoCircuit will in the future use
symbolic analysis like Orora, stay tuned.
- Daniel Payne, Consultant
NeoLinear:
NeoLinear NeoCell is making new inroads. In the new incarnation the
tools will have an integrated database for constraints. Until now
they were written in a specific cumbersome environment. Now they
move to a centralized domain. Constraints can be introduced in
schematic, layout, or text environment. All of them will reside in
the database and can viewed as polygons or exported as text. The tool
has pre-placement capabilities to define specific structures like the
CiraNova, centroid and symmetry, including local routing.
The fact that now you can add on-line constraints in layout and the
compactors VLO/VLM can use them for compaction purposes and maintain
them is a really big step toward my idea of a full custom flow. The
biggest new direction of NeoCell is to make the placement and routing
back annotated to schematic in NeoCircuit who then will optimize
design based on layout realities (parasitic data). It looks like an
"in-place optimization" that the Place & Route people took advantage
for the last 10 years. A refreshing initiative that I still want to
see implemented.
- Dan Clein, author of "CMOS IC Layout"
Our analog design guys don't have faith in tools like NeoCell.
Granted, analog designers normally don't trust any automation tools,
but with NeoCell, after the consolidation, our Cadence sales contact
seems to avoid pushing this tool to us, which to us means Cadence
doesn't have a lot of confidence in their own NeoCell either.
- [ An Anon Engineer ]
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