( DAC 11 Item 9 ) ----------------------------------------------- [10/13/11]

Subject: Amiq DVT Eclipse, Atrenta Spyglass, Duolog Bitwise, EVE Zebu

SIDESHOWS: It appears that VCS/NC-sim/ModelTech have gone commodity because
no one noticed anything they showed at this DAC.  Instead it was the odd
side niche tools like Amiq DVT Eclipse, Atrenta Spyglass, Duolog Bitwise,
that caught user's mindshare in the Verilog/VHDL simulation space.

Oh, and one honorable mention to goes to the Eve Zebu emulator...

     "What were the 3 or 4 most INTERESTING specific tools that
      you saw at DAC this year?  WHY where they interesting to you?"

         ----    ----    ----    ----    ----    ----   ----

   2) Amiq DVT Eclipse for 'e' and System Verilog: I had not realized
      that I had been developing code by banging rocks together.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   1) Cadence Virtual System Platform was a new contender in the virtual
      prototyping space.

   2) Amiq DVT for verification engineers working with e and System Verilog.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   Amiq DVT Eclipse.

   I have been playing with this editor.  It is tailored for System Verilog
   and particularly for OVM/UVM.   It's extremely powerful is time saving.

   This tool was clearly developed by users themselves (not just requirement
   people).

   DVT Eclipse does dynamic code check on the fly, linting for SystemVerilog
   and linting for OVM/UVM, choice of editors (e.g., emacs), does context
   sensitive references to where objects are used, templates, OVM/UVM
   compliance checks with warnings and error IDs and links to them, auto
   macro inclusion on selected preferences, class diagram creation with
   options of details, links to user define tags in code.

   It's very VERY powerful and is a great aid in development/debugging of
   design and verification code (and not just for SystemVerilog, as it also
   supports VHDL.

       - Ben Cohen, well known author of VHDL and SVA books

         ----    ----    ----    ----    ----    ----   ----

   Synopsys may jump on UVM and Cadence may jump on UPF 2.0.  Single
   standards, here we come.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   Atrenta Spyglass can be a very useful tool for identifying problem in
   a design early in the cycle.  Their physical estimation technology could
   be quite useful early on.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   I attended the SpyGlass-DFT MBIST presentation and found it is the
   most interesting to me.

   It does proprietary MBIST IP insertion.  We are facing a lot problems
   to insert MBIST for 1000's of memories.  It impacts timing closure,
   power closure, repair/run time optimization, and diagnostics support,
   etc.  SpyGlass-DFT MBIST is a good tool to manipulate RTL insertion
   hierarchy, IP connections, and BIST sharing.

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   Semifore CSR Compiler, Duolog Bitwise, Atrenta 1Team-Genesis Registers

       - Gary Stringham & Associates, LLC

         ----    ----    ----    ----    ----    ----   ----

   Atrenta GenSys

       - [ An Anon Engineer ]

         ----    ----    ----    ----    ----    ----   ----

   3) Eve Zebu emulator - They have picked up and look like they got a
      proven product now.  That would boost the verification.

       - [ An Anon Engineer ]
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